55 lines
1.4 KiB
Verilog
55 lines
1.4 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:06:25 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap64_getBase O 32
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// wrap64_getBase_cap I 115
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//
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// Combinational paths from inputs to outputs:
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// wrap64_getBase_cap -> wrap64_getBase
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap64_getBase(wrap64_getBase_cap,
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wrap64_getBase);
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// value method wrap64_getBase
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input [114 : 0] wrap64_getBase_cap;
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output [31 : 0] wrap64_getBase;
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// signals for module outputs
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wire [31 : 0] wrap64_getBase;
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// remaining internal signals
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wire [31 : 0] addBase__h64;
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wire [23 : 0] mask__h65;
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wire [9 : 0] x__h167;
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// value method wrap64_getBase
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assign wrap64_getBase =
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{ wrap64_getBase_cap[113:90] & mask__h65, 8'd0 } + addBase__h64 ;
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// remaining internal signals
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assign addBase__h64 =
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{ {22{x__h167[9]}}, x__h167 } << wrap64_getBase_cap[31:26] ;
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assign mask__h65 = 24'd16777215 << wrap64_getBase_cap[31:26] ;
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assign x__h167 = { wrap64_getBase_cap[1:0], wrap64_getBase_cap[17:10] } ;
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endmodule // module_wrap64_getBase
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