60 lines
1.6 KiB
Verilog
60 lines
1.6 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:06:25 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap64_getKind O 7
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// wrap64_getKind_cap I 115
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//
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// Combinational paths from inputs to outputs:
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// wrap64_getKind_cap -> wrap64_getKind
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap64_getKind(wrap64_getKind_cap,
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wrap64_getKind);
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// value method wrap64_getKind
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input [114 : 0] wrap64_getKind_cap;
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output [6 : 0] wrap64_getKind;
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// signals for module outputs
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wire [6 : 0] wrap64_getKind;
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// remaining internal signals
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reg [2 : 0] CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1;
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// value method wrap64_getKind
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assign wrap64_getKind =
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{ CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1,
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wrap64_getKind_cap[60:57] } ;
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// remaining internal signals
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always@(wrap64_getKind_cap)
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begin
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case (wrap64_getKind_cap[60:57])
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4'd12: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd3;
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4'd13: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd2;
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4'd14: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd1;
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4'd15: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd0;
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default: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd4;
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endcase
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end
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endmodule // module_wrap64_getKind
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