58 lines
1.5 KiB
Verilog
58 lines
1.5 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:06:25 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap64_getLength O 33
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// wrap64_getLength_cap I 115
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//
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// Combinational paths from inputs to outputs:
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// wrap64_getLength_cap -> wrap64_getLength
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap64_getLength(wrap64_getLength_cap,
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wrap64_getLength);
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// value method wrap64_getLength
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input [114 : 0] wrap64_getLength_cap;
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output [32 : 0] wrap64_getLength;
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// signals for module outputs
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wire [32 : 0] wrap64_getLength;
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// remaining internal signals
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wire [32 : 0] length__h66;
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wire [9 : 0] base__h65, top__h64, x__h125;
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// value method wrap64_getLength
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assign wrap64_getLength =
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(wrap64_getLength_cap[31:26] < 6'd26) ?
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length__h66 :
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33'h1FFFFFFFF ;
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// remaining internal signals
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assign base__h65 =
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{ wrap64_getLength_cap[1:0], wrap64_getLength_cap[17:10] } ;
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assign length__h66 = { 23'd0, x__h125 } << wrap64_getLength_cap[31:26] ;
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assign top__h64 =
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{ wrap64_getLength_cap[3:2], wrap64_getLength_cap[25:18] } ;
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assign x__h125 = top__h64 - base__h65 ;
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endmodule // module_wrap64_getLength
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