57 lines
1.6 KiB
Verilog
57 lines
1.6 KiB
Verilog
//
|
|
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
|
|
//
|
|
// On Tue Feb 17 13:06:25 GMT 2026
|
|
//
|
|
//
|
|
// Ports:
|
|
// Name I/O size props
|
|
// wrap64_getOffset O 32
|
|
// wrap64_getOffset_cap I 115
|
|
//
|
|
// Combinational paths from inputs to outputs:
|
|
// wrap64_getOffset_cap -> wrap64_getOffset
|
|
//
|
|
//
|
|
|
|
`ifdef BSV_ASSIGNMENT_DELAY
|
|
`else
|
|
`define BSV_ASSIGNMENT_DELAY
|
|
`endif
|
|
|
|
`ifdef BSV_POSITIVE_RESET
|
|
`define BSV_RESET_VALUE 1'b1
|
|
`define BSV_RESET_EDGE posedge
|
|
`else
|
|
`define BSV_RESET_VALUE 1'b0
|
|
`define BSV_RESET_EDGE negedge
|
|
`endif
|
|
|
|
module module_wrap64_getOffset(wrap64_getOffset_cap,
|
|
wrap64_getOffset);
|
|
// value method wrap64_getOffset
|
|
input [114 : 0] wrap64_getOffset_cap;
|
|
output [31 : 0] wrap64_getOffset;
|
|
|
|
// signals for module outputs
|
|
wire [31 : 0] wrap64_getOffset;
|
|
|
|
// remaining internal signals
|
|
wire [31 : 0] addrLSB__h68, x__h204, x__h79, x__h81, y__h203;
|
|
wire [9 : 0] base__h66, offset__h67;
|
|
|
|
// value method wrap64_getOffset
|
|
assign wrap64_getOffset = x__h79 | addrLSB__h68 ;
|
|
|
|
// remaining internal signals
|
|
assign addrLSB__h68 = wrap64_getOffset_cap[113:82] & y__h203 ;
|
|
assign base__h66 =
|
|
{ wrap64_getOffset_cap[1:0], wrap64_getOffset_cap[17:10] } ;
|
|
assign offset__h67 = { 2'b0, wrap64_getOffset_cap[81:74] } - base__h66 ;
|
|
assign x__h204 = 32'hFFFFFFFF << wrap64_getOffset_cap[31:26] ;
|
|
assign x__h79 = x__h81 << wrap64_getOffset_cap[31:26] ;
|
|
assign x__h81 = { {22{offset__h67[9]}}, offset__h67 } ;
|
|
assign y__h203 = ~x__h204 ;
|
|
endmodule // module_wrap64_getOffset
|
|
|