42 lines
969 B
Verilog
42 lines
969 B
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:06:25 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap64_getSoftPerms O 16 const
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// wrap64_getSoftPerms_cap I 115 unused
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap64_getSoftPerms(wrap64_getSoftPerms_cap,
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wrap64_getSoftPerms);
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// value method wrap64_getSoftPerms
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input [114 : 0] wrap64_getSoftPerms_cap;
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output [15 : 0] wrap64_getSoftPerms;
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// signals for module outputs
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wire [15 : 0] wrap64_getSoftPerms;
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// value method wrap64_getSoftPerms
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assign wrap64_getSoftPerms = 16'd0 ;
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endmodule // module_wrap64_getSoftPerms
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