75 lines
2.1 KiB
Verilog
75 lines
2.1 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:06:25 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap64_getTop O 33
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// wrap64_getTop_cap I 115
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//
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// Combinational paths from inputs to outputs:
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// wrap64_getTop_cap -> wrap64_getTop
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap64_getTop(wrap64_getTop_cap,
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wrap64_getTop);
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// value method wrap64_getTop
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input [114 : 0] wrap64_getTop_cap;
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output [32 : 0] wrap64_getTop;
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// signals for module outputs
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wire [32 : 0] wrap64_getTop;
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// remaining internal signals
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wire [32 : 0] addTop__h64, result__h512, ret__h66;
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wire [24 : 0] mask__h65;
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wire [23 : 0] wrap64_getTop_cap_BITS_113_TO_90_PLUS_SEXT_wra_ETC__q2;
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wire [9 : 0] x__h178;
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wire [1 : 0] wrap64_getTop_cap_BITS_1_TO_0__q1;
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// value method wrap64_getTop
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assign wrap64_getTop =
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(wrap64_getTop_cap[31:26] < 6'd25 &&
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ret__h66[32:31] -
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{ 1'b0,
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(wrap64_getTop_cap[31:26] == 6'd24) ?
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wrap64_getTop_cap[17] :
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wrap64_getTop_cap_BITS_113_TO_90_PLUS_SEXT_wra_ETC__q2[23] } >
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2'd1) ?
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result__h512 :
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ret__h66 ;
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// remaining internal signals
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assign addTop__h64 =
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{ {23{x__h178[9]}}, x__h178 } << wrap64_getTop_cap[31:26] ;
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assign mask__h65 = 25'd33554431 << wrap64_getTop_cap[31:26] ;
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assign result__h512 = { ~ret__h66[32], ret__h66[31:0] } ;
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assign ret__h66 =
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{ { 1'b0, wrap64_getTop_cap[113:90] } & mask__h65, 8'd0 } +
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addTop__h64 ;
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assign wrap64_getTop_cap_BITS_113_TO_90_PLUS_SEXT_wra_ETC__q2 =
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wrap64_getTop_cap[113:90] +
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({ {22{wrap64_getTop_cap_BITS_1_TO_0__q1[1]}},
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wrap64_getTop_cap_BITS_1_TO_0__q1 } <<
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wrap64_getTop_cap[31:26]) ;
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assign wrap64_getTop_cap_BITS_1_TO_0__q1 = wrap64_getTop_cap[1:0] ;
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assign x__h178 = { wrap64_getTop_cap[3:2], wrap64_getTop_cap[25:18] } ;
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endmodule // module_wrap64_getTop
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