67 lines
1.9 KiB
Verilog
67 lines
1.9 KiB
Verilog
//
|
|
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
|
|
//
|
|
// On Tue Feb 17 13:06:26 GMT 2026
|
|
//
|
|
//
|
|
// Ports:
|
|
// Name I/O size props
|
|
// wrap64_toMem O 89
|
|
// wrap64_toMem_cap I 115
|
|
//
|
|
// Combinational paths from inputs to outputs:
|
|
// wrap64_toMem_cap -> wrap64_toMem
|
|
//
|
|
//
|
|
|
|
`ifdef BSV_ASSIGNMENT_DELAY
|
|
`else
|
|
`define BSV_ASSIGNMENT_DELAY
|
|
`endif
|
|
|
|
`ifdef BSV_POSITIVE_RESET
|
|
`define BSV_RESET_VALUE 1'b1
|
|
`define BSV_RESET_EDGE posedge
|
|
`else
|
|
`define BSV_RESET_VALUE 1'b0
|
|
`define BSV_RESET_EDGE negedge
|
|
`endif
|
|
|
|
module module_wrap64_toMem(wrap64_toMem_cap,
|
|
wrap64_toMem);
|
|
// value method wrap64_toMem
|
|
input [114 : 0] wrap64_toMem_cap;
|
|
output [88 : 0] wrap64_toMem;
|
|
|
|
// signals for module outputs
|
|
wire [88 : 0] wrap64_toMem;
|
|
|
|
// remaining internal signals
|
|
wire [87 : 0] x__h467;
|
|
wire [13 : 0] IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15;
|
|
|
|
// value method wrap64_toMem
|
|
assign wrap64_toMem = { wrap64_toMem_cap[114], x__h467 } ;
|
|
|
|
// remaining internal signals
|
|
assign IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15 =
|
|
wrap64_toMem_cap[32] ?
|
|
{ wrap64_toMem_cap[23:21],
|
|
wrap64_toMem_cap[31:29],
|
|
wrap64_toMem_cap[17:13],
|
|
wrap64_toMem_cap[28:26] } :
|
|
wrap64_toMem_cap[23:10] ;
|
|
assign x__h467 =
|
|
{ wrap64_toMem_cap[73:61],
|
|
~wrap64_toMem_cap[60:57],
|
|
24'hAAAAAA ^ 24'hAAAAAA,
|
|
~wrap64_toMem_cap[32],
|
|
IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[13:10],
|
|
~IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[9:8],
|
|
IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[7:2],
|
|
~IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[1],
|
|
IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[0],
|
|
wrap64_toMem_cap[113:82] } ;
|
|
endmodule // module_wrap64_toMem
|
|
|