46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:06:26 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap64_validAsType O 1
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// wrap64_validAsType_dummy I 115 unused
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// wrap64_validAsType_checkType I 32
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//
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// Combinational paths from inputs to outputs:
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// wrap64_validAsType_checkType -> wrap64_validAsType
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap64_validAsType(wrap64_validAsType_dummy,
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wrap64_validAsType_checkType,
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wrap64_validAsType);
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// value method wrap64_validAsType
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input [114 : 0] wrap64_validAsType_dummy;
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input [31 : 0] wrap64_validAsType_checkType;
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output wrap64_validAsType;
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// signals for module outputs
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wire wrap64_validAsType;
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// value method wrap64_validAsType
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assign wrap64_validAsType = wrap64_validAsType_checkType <= 32'd11 ;
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endmodule // module_wrap64_validAsType
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