a6664e512c
Uses argparse's "choices" argument, remove unused method and use abc and for abstract methods. Also updates the python filename in the Makefile
236 lines
9.0 KiB
Python
Executable File
236 lines
9.0 KiB
Python
Executable File
#! /usr/bin/env python3
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import argparse
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import re
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from abc import ABC, abstractmethod
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parser = argparse.ArgumentParser(description=
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'''Generates a Blarney wrapper for the given Bluespec generated verilog file
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containing a module definition of a purely combinational CHERI function.
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''')
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parser.add_argument('verilog_files', metavar='VERILOG_FILE', type=str, nargs='+',
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help='The file(s) to process')
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parser.add_argument('--output', '-o', metavar='OUTPUT_FILE', type=str, nargs='?',
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default="",
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help='The output Blarney Haskell module to generate')
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parser.add_argument('--generator', metavar='GENERATOR', type=str, nargs='?',
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choices=['blarney','sv','systemverilog'], default='blarney',
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help='The generator to be used')
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args = parser.parse_args()
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# Generic wrapper for a Verilog module
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class Wrapper:
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def __init__(self, size, name, ins, out):
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self.size = size
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self.name = name
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self.ins = ins
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self.out = out
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def verilogModuleName(self):
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return "module_wrap{:d}_{:s}".format(self.size, self.name)
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def verilogInputNames(self):
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return ["wrap{:d}_{:s}_{:s}".format(self.size, self.name, nm)
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for nm in [x[0] for x in self.ins]]
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def verilogOutputName(self):
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return "wrap{:d}_{:s}".format(self.size, self.name)
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# Generic generator class
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# Describes the minimum functionality that a generator needs to implement.
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# A generator takes some list of Verilog modules (which includes information
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# about the module name, inputs, outputs, etc) and generates a list of file
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# contents that should be written.
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class Generator(ABC):
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# namehint is a hint for naming, and each specific generator subclass will
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# interpret it in its own way. In many cases it may be the single generated
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# filename
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def __init__(self, namehint, mods = None):
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self.namehint = namehint
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if mods is not None:
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self.modules = mods
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else:
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self.modules = list()
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def addVerilogModule(self, mod):
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self.modules.append(mod)
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# Generates a list of tuples containing output file names and output file
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# contents to be written to disk
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@abstractmethod
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def emit(self):
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pass
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# Generates Blarney files
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# When the namehint is not empty, it is used as the filename and .hs is appended
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# otherwise the old default filename of CHERIBlarneyWrappers.hs is used
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class BlarneyGenerator(Generator):
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def emit(self):
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modname = "CHERIBlarneyWrappers"
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filename = modname + ".hs"
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if self.namehint is not None and self.namehint != "":
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modname = self.namehint
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filename = self.namehint + ".hs"
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contents = "module " + modname + " where\n\n"
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contents += "import Blarney\n"
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contents += "import Blarney.Core.BV\n"
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for mod in self.modules:
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print(mod.name)
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contents += "\n"
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ins_names = [x[0] for x in mod.ins]
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ins_wdths = [x[1] for x in mod.ins]
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str_type = "{:s} :: {:s}{:s}{:s}".format(
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mod.name,
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" -> ".join(["Bit {:d}".format(n) for n in ins_wdths]),
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" -> " if mod.ins else "",
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"Bit {:d}".format(mod.out[1]))
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str_decl = "{:s} {:s} = FromBV $\n makePrim1 (Custom \"{:s}\" [{:s}] [{:s}] [] False Nothing) [{:s}]".format(
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mod.name, " ".join(ins_names),
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mod.verilogModuleName(),
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", ".join(["(\"{:s}\", {:d})".format(n, w)
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for (n, w) in zip(mod.verilogInputNames(),
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ins_wdths)]),
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"(\"{:s}\", {:d})".format(mod.verilogOutputName(), mod.out[1]),
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", ".join(["toBV {:s}".format(nm) for nm in ins_names]))
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contents += "{:s}\n{:s}".format(str_type, str_decl)
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contents += "\n".format(str_decl)
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return [(filename, contents)]
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# generates SystemVerilog files
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# when the namehint is non-empty it is used as a prefix for the file name
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# generates a _pkg.sv file containing:
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# a typedef of cheri_cap_t which is an "opaque" capability
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# a typedef of cheri_cap_dec_t which is a decompressed capability
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# generates a _mod.sv file containing a module which combinationally takes an "opaque"
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# capability as the input and gives a decompressed capability as the output
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class SystemVerilogGenerator(Generator):
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def emit(self):
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cap_type_name = "cheri_cap_t" # the name of the opaque cap type
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cap_dec_type_name = "cheri_cap_dec_t" # the name of the expanded cap type
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cap_dec_mod_name = "cheri_cap_expander" # the name of the expanding module
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cap_in_signal_name = "cap_i" # the name of the input signal to the expanding module
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cap_out_signal_name = "cap_o" # the name of the output signal to the expanding module
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cap_search_string = "cap" # the string required for inferring capability width
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pkg_file_name = "cheri_pkg.sv"
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module_file_name = "{:s}.sv".format(cap_dec_mod_name)
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# prepend namehint if non-empty
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if self.namehint is not None and self.namehint != "":
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pkg_file_name = self.namehint + "_" + pkg_file_name
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module_file_name = self.namehint + "_" + module_file_name
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pkg_name = pkg_file_name[:-3]
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dec_mod_name = module_file_name[:-3]
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# find the size of a capability by assuming that any no-input modules
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# with "cap" in the name have a capability output
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cap_size = None
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for mod in self.modules:
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if len(mod.ins) != 0 or cap_search_string not in mod.name.lower():
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continue
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cap_size = mod.out[1]
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break
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if cap_size == None:
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# the above method failed to find a capability size
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# to fix, can either implement a better method or just hard-code the capability size
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raise NotImplementedError("Unable to determine capability size from input files")
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cap_type_def_text = " typedef logic [{:d}:0] {:s};\n".format(cap_size-1, cap_type_name)
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# assume all modules with one capability-sized input are "getters"
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# these will be the fields of the decompressed capability struct
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struct_elems = list()
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for mod in self.modules:
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if len(mod.ins) == 1 and mod.ins[0][1] == cap_size:
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struct_elems.append(mod)
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# structure definition
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struct_def_text = " typedef struct packed {\n"
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for mod in struct_elems:
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struct_def_text += " logic [{:d}:{:d}] {:s};\n".format(mod.out[1]-1, 0, mod.name)
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struct_def_text += " }} {:s};\n".format(cap_dec_type_name)
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# package definition
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pkg_def_text = "package {:s};\n".format(pkg_name)
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pkg_def_text += cap_type_def_text
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pkg_def_text += struct_def_text
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pkg_def_text += "endpackage\n"
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# module definition
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module_def_text = "module {:s} (\n".format(cap_dec_mod_name)
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module_def_text += " input {:s}::{:s} {:s},\n".format(pkg_name, cap_type_name, cap_in_signal_name)
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module_def_text += " output {:s}::{:s} {:s}\n".format(pkg_name, cap_dec_type_name, cap_out_signal_name)
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module_def_text += ");\n"
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module_def_text += " import {:s}::*;\n".format(pkg_name)
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# module instantiations
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for mod in struct_elems:
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module_def_text += " {:s} {:s}_mod (\n".format(mod.verilogModuleName(), mod.name)
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module_def_text += " .{:s}({:s}),\n".format(mod.verilogInputNames()[0], cap_in_signal_name)
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module_def_text += " .{:s}({:s}.{:s})\n".format(mod.verilogOutputName(), cap_out_signal_name, mod.name)
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module_def_text += " );\n"
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module_def_text += "endmodule\n"
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return [(pkg_file_name, pkg_def_text),
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(module_file_name, module_def_text)]
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def main():
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# define module regexp
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modDecl = re.compile("^module\s+module_wrap(\d+)_(\w+)\(")
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# TODO handle size 1
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#
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# gather the list of modules
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wrappers = []
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for fname in args.verilog_files:
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size = 0
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name = None
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ins = []
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out = ("",0)
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with open(fname, "r") as f:
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for ln in f:
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modM = modDecl.match(ln)
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if modM:
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size = int(modM.group(1))
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name = modM.group(2)
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break
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if not name:
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print("Couldn't find a valid Verilog module definition")
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exit(-1)
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# define input/output regexp
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inDecl = re.compile("^\s*input(\s+\[(\d+)\s+:\s+0\])?\s+wrap(\d+)_"+name+"_(\w+);")
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outDecl = re.compile("^\s*output(\s+\[(\d+)\s+:\s+0\])?\s+wrap(\d+)_"+name+";")
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for ln in f:
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inM = inDecl.match(ln)
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outM = outDecl.match(ln)
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if inM:
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ins.append((inM.group(4), (int(inM.group(2)) + 1) if inM.group(1) else 1))
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elif outM:
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out = (name, (int(outM.group(2)) + 1) if outM.group(1) else 1)
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#else:
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# print("===>> no match for line: {:s}".format(ln))
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wrappers.append(Wrapper(size, name, ins, out))
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# choose the right generator based on the input argument
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gen = None
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if args.generator.lower() in ["systemverilog", "sv"]:
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gen = SystemVerilogGenerator(args.output, wrappers)
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elif args.generator.lower() in ["blarney"]:
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gen = BlarneyGenerator(args.output, wrappers)
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else:
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print("Invalid generator selected; exiting")
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return
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for out in gen.emit():
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with open(out[0], "w") as f:
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f.write(out[1])
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if __name__ == "__main__":
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main()
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