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<meta name=keywords content="RISCV,Open Source"><meta name=description content="Basics of what is RISC-V"><meta name=author content="Akilan Selvacoumar"><link rel=canonical href=http://localhost:1313/technicalposts/riscv/><link crossorigin=anonymous href=/assets/css/stylesheet.f49d66caae9ea0fd43f21f29e71a8d3e284517ed770f2aa86fa012953ad3c9ef.css integrity="sha256-9J1myq6eoP1D8h8p5xqNPihFF+13Dyqob6ASlTrTye8=" rel="preload stylesheet" as=style><link rel=icon href=http://localhost:1313/favicon.ico><link rel=icon type=image/png sizes=16x16 href=http://localhost:1313/favicon-16x16.png><link rel=icon type=image/png sizes=32x32 href=http://localhost:1313/favicon-32x32.png><link rel=apple-touch-icon href=http://localhost:1313/apple-touch-icon.png><link rel=mask-icon href=http://localhost:1313/safari-pinned-tab.svg><meta name=theme-color content="#2e2e33"><meta name=msapplication-TileColor content="#2e2e33"><link rel=alternate hreflang=en href=http://localhost:1313/technicalposts/riscv/><noscript><style>#theme-toggle,.top-link{display:none}</style><style>@media(prefers-color-scheme:dark){:root{--theme:rgb(29, 30, 32);--entry:rgb(46, 46, 51);--primary:rgb(218, 218, 219);--secondary:rgb(155, 156, 157);--tertiary:rgb(65, 66, 68);--content:rgb(196, 196, 197);--code-block-bg:rgb(46, 46, 51);--code-bg:rgb(55, 56, 62);--border:rgb(51, 51, 51)}.list{background:var(--theme)}.list:not(.dark)::-webkit-scrollbar-track{background:0 0}.list:not(.dark)::-webkit-scrollbar-thumb{border-color:var(--theme)}}</style></noscript><meta property="og:url" content="http://localhost:1313/technicalposts/riscv/"><meta property="og:site_name" content="Akilan"><meta property="og:title" content="Challenging myself to understand RISC-V"><meta property="og:description" content="Basics of what is RISC-V"><meta property="og:locale" content="en"><meta property="og:type" content="article"><meta property="article:section" content="technicalposts"><meta property="article:published_time" content="2021-05-30T00:00:00+00:00"><meta property="article:modified_time" content="2021-05-30T00:00:00+00:00"><meta property="article:tag" content="RISCV"><meta property="article:tag" content="Open Source"><meta name=twitter:card content="summary"><meta name=twitter:title content="Challenging myself to understand RISC-V"><meta name=twitter:description content="Basics of what is RISC-V"><script type=application/ld+json>{"@context":"https://schema.org","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"name":"Technical Posts","item":"http://localhost:1313/technicalposts/"},{"@type":"ListItem","position":2,"name":"Challenging myself to understand RISC-V","item":"http://localhost:1313/technicalposts/riscv/"}]}</script><script type=application/ld+json>{"@context":"https://schema.org","@type":"BlogPosting","headline":"Challenging myself to understand RISC-V","name":"Challenging myself to understand RISC-V","description":"Basics of what is RISC-V","keywords":["RISCV","Open Source"],"articleBody":"Why do we need open standards for CPU Architecture ? We want to allow users to see all the parts of the architecture without any proprietary constraints. We want to have the rights to modify and distribute without paying any licensing fees and constraints in sharing. With open standards it’s easier to build on top of others work and possibly build CPU designs custom made for certain tasks. What is RISC-V ? RISC-V is just an open source ISA (Instruction Set Architecture). An ISA is the software interface for the hardware. A single ISA can have many hardware implementations. In technical terms as ISA defines set of Instructions and how they behave such as:\nData types Registers Addressing modes memory models Protection levels How is I/O are done Virtual memory Exceptions Another important factor to understand is that RISC-V is a standard and not an implementation. This means that the entire ISA is defined in a huge latex file which can be found on Github.\nRepo link: https://github.com/riscv/riscv-isa-manual\nThe RISC-V is a well organized ISA and is divided into various categories and extensions in order to keep it as a modular design. The RISC-V is maintained the non profit organization called RISC-V foundation.\n“RISC-V in contrast was made specifically to be easy to teach while pragmatic enough to actually allow the implementation of high performance microprocessors.” Few companies working on RISC-V NVIDIA: using RISC-V in it’s GPU SiFive: Startup that allows you to create your own RISC-V board or use exsisting models they provide with great toolkits around them. Western Digital: Focusing on building custom RISC-V cores. Complier support for RISC-V ISA GCC LLVM/Clang glibc Go Rust How is the RISC-V ISA organized In this section we look into how RISC-V is organised\nRV N (Extension letter) RV stands for RISC-V N - Number of bits (Ex: 32 bits) Extension letter: This is the Extension for the instruction sets (I stands for Integer) Example Base ISA RV32I, RV64I, RV128I\nStandard Extensions M: Math A: Atomic F: Floating Point D: Double Precision Floating Point - G: General Purpose (Includes, Integer, Math, Atomic, Floating Point and Double Precision Floating Point) Linux supports RV64G This is called as RISC-V 64 bit General Purpose\nLets talk a bit indepth of RV32I RV32I is a base ISA and the easiest to understand. RV32I means it’s RISC-V 32 bit Integer ISA.\nRegisters: x0-x31 (x0 is hardwired to 0) Each register is 32 bits which can be called as 1 word.\nFig 1.0 Simplified schematics of RV32I\nNow we will recall the basics and try to understand how to read an instruction.\nadd rd,rs1,rs2 add: is the opcode rd: is the destination register rs1: Source register 1 rs2: Source register 2 Fig 1.1 Assembly instructions for RV32I\nFig 1.2 Registers for RV32I\nInteresting research papers Implementing RISC-V System-on-Chip for Acceleration of Convolution Operation and Activation Function Based on FPGA (Field programmable gate arrays): FGPA are mostly for application specific integrated circuits. An example would be Intel using FGPA to prototype new chips. The objective of the paper was to design a RISC-V processor for specific tasks such as Convolution functions and activation functions. The result was that the RISC-V processor was faster than CPU + co-processor mode and used lesser than the CPU + GPU mode.\nTowards deep learning using Tensorflow lite on RISC-V: This paper focuses on ISA extensions customized for machine learning kernels. The software infrastructure implemented was optimized for neural network execution. The following was integrated into Tensorflow lite. The result was that instructions was reduced by 8X.\nA compiler comparison in the RISC-V ecosystem: Comparing LLVM and GCC performance on RISC-V. LLVM and GCC produce same binary size but both have different execution times.\nInteresting Open Source projects RISCBoy: It is an open-source portable games console, designed from scratch. RISC-V compatible CPU. Has raster graphics pipelines and display controllers. It consists of other infrastructure such as memory controllers and GPIO ports. It also consists of a CAD design of the PCB layout. Potato: The Potato Processor is a simple RISC-V processor written in VHDL for use in FPGAs. It implements the 32-bit integer subset of the RISC-V Specification version 2.0. Vulcan: RISC-V instruction set simulation built for education using flutter. ","wordCount":"707","inLanguage":"en","datePublished":"2021-05-30T00:00:00Z","dateModified":"2021-05-30T00:00:00Z","author":{"@type":"Person","name":"Akilan Selvacoumar"},"mainEntityOfPage":{"@type":"WebPage","@id":"http://localhost:1313/technicalposts/riscv/"},"publisher":{"@type":"Organization","name":"Akilan","logo":{"@type":"ImageObject","url":"http://localhost:1313/favicon.ico"}}}</script></head><body id=top><script>localStorage.getItem("pref-theme")==="dark"?document.body.classList.add("dark"):localStorage.getItem("pref-theme")==="light"?document.body.classList.remove("dark"):window.matchMedia("(prefers-color-scheme: dark)").matches&&document.body.classList.add("dark")</script><header class=header><nav class=nav><div class=logo><a href=http://localhost:1313/ accesskey=h title="Akilan (Alt + H)">Akilan</a><div class=logo-switches><button id=theme-toggle accesskey=t title="(Alt + T)" aria-label="Toggle theme"><svg id="moon" width="24" height="18" viewBox="0 0 24 24" fill="none" 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target=_blank>Suggest Changes</a></div></header><div class=toc><details><summary accesskey=c title="(Alt + C)"><span class=details>Table of Contents</span></summary><div class=inner><ul><li><a href=#why-do-we-need-open-standards-for-cpu-architecture- aria-label="Why do we need open standards for CPU Architecture ?">Why do we need open standards for CPU Architecture ?</a></li><li><a href=#what-is-risc-v- aria-label="What is RISC-V ?">What is RISC-V ?</a><ul><li><a href=#heading aria-label="“RISC-V in contrast was made specifically to be easy to teach while pragmatic enough to actually allow the implementation of high performance microprocessors.”">“RISC-V in contrast was made specifically to be easy to teach while pragmatic enough to actually allow the implementation of high performance microprocessors.”</a></li></ul></li><li><a href=#few-companies-working-on-risc-v aria-label="Few companies working on RISC-V">Few companies working on RISC-V</a></li><li><a href=#complier-support-for-risc-v-isa aria-label="Complier support for RISC-V ISA">Complier support for RISC-V ISA</a></li><li><a href=#how-is-the-risc-v-isa-organized aria-label="How is the RISC-V ISA organized">How is the RISC-V ISA organized</a><ul><li><a href=#rv-n-extension-letter aria-label="RV N (Extension letter)">RV N (Extension letter)</a></li><li><a href=#example-base-isa aria-label="Example Base ISA">Example Base ISA</a></li><li><a href=#standard-extensions aria-label="Standard Extensions">Standard Extensions</a><ul><li><a href=#--g-general-purpose-includes-integer-math-atomic-floating-point-and-double-precision-floating-point aria-label="- G: General Purpose (Includes, Integer, Math, Atomic, Floating Point and Double Precision Floating Point)">- G: General Purpose (Includes, Integer, Math, Atomic, Floating Point and Double Precision Floating Point)</a></li></ul></li><li><a href=#linux-supports aria-label="Linux supports">Linux supports</a><ul><li><a href=#rv64g aria-label=RV64G>RV64G</a></li></ul></li></ul></li><li><a href=#lets-talk-a-bit-indepth-of-rv32i aria-label="Lets talk a bit indepth of RV32I">Lets talk a bit indepth of RV32I</a></li><li><a href=#interesting-research-papers aria-label="Interesting research papers">Interesting research papers</a></li><li><a href=#interesting-open-source-projects aria-label="Interesting Open Source projects">Interesting Open Source projects</a></li></ul></div></details></div><div class=post-content><h2 id=why-do-we-need-open-standards-for-cpu-architecture->Why do we need open standards for CPU Architecture ?<a hidden class=anchor aria-hidden=true href=#why-do-we-need-open-standards-for-cpu-architecture->#</a></h2><ul><li>We want to allow users to see all the parts of the architecture
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without any proprietary constraints.</li><li>We want to have the rights to modify and distribute without paying any licensing fees and constraints in sharing.</li><li>With open standards it’s easier to build on top of others work and possibly build CPU designs custom made for certain tasks.</li></ul><h2 id=what-is-risc-v->What is RISC-V ?<a hidden class=anchor aria-hidden=true href=#what-is-risc-v->#</a></h2><p>RISC-V is just an open source ISA (Instruction Set Architecture). An ISA is the software interface for the hardware. A single ISA can
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have many hardware implementations. In technical terms as ISA defines set of Instructions and how they behave such as:</p><ul><li>Data types</li><li>Registers</li><li>Addressing modes</li><li>memory models</li><li>Protection levels</li><li>How is I/O are done</li><li>Virtual memory</li><li>Exceptions</li></ul><p>Another important factor to understand is that RISC-V is a standard
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and not an implementation. This means that the entire ISA is defined in a huge latex file which can be found on Github.</p><p>Repo link: <a href=https://github.com/riscv/riscv-isa-manual>https://github.com/riscv/riscv-isa-manual</a></p><p>The RISC-V is a well organized ISA and is divided into various categories and extensions in order to keep it as a modular design.
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The RISC-V is maintained the non profit organization called <a href=https://riscv.org/>RISC-V foundation</a>.</p><h3 id=heading><a href=https://medium.com/swlh/risc-v-assembly-for-beginners-387c6cd02c49>“RISC-V in contrast was made specifically to be easy to teach while pragmatic enough to actually allow the implementation of high performance microprocessors.”</a><a hidden class=anchor aria-hidden=true href=#heading>#</a></h3><h2 id=few-companies-working-on-risc-v>Few companies working on RISC-V<a hidden class=anchor aria-hidden=true href=#few-companies-working-on-risc-v>#</a></h2><ul><li><a href=https://riscv.org/wp-content/uploads/2017/05/Tue1345pm-NVIDIA-Sijstermans.pdf>NVIDIA</a>: using RISC-V in it’s GPU</li><li><a href=https://www.sifive.com/>SiFive</a>: Startup that allows you to create your own RISC-V board or use exsisting models they provide with great toolkits around them.</li><li><a href=https://blog.westerndigital.com/risc-v-swerv-core-open-source/>Western Digital</a>: Focusing on building custom
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RISC-V cores.</li></ul><h2 id=complier-support-for-risc-v-isa>Complier support for RISC-V ISA<a hidden class=anchor aria-hidden=true href=#complier-support-for-risc-v-isa>#</a></h2><ul><li><a href=https://github.com/riscv/riscv-gnu-toolchain>GCC</a></li><li><a href=https://github.com/sifive/riscv-llvm>LLVM/Clang</a></li><li><a href="https://sourceware.org/git/?p=glibc.git">glibc</a></li><li><a href=https://github.com/riscvarchive/riscv-go>Go</a></li><li><a href=https://github.com/riscv-rust/riscv-rust-quickstart>Rust</a></li></ul><h2 id=how-is-the-risc-v-isa-organized>How is the RISC-V ISA organized<a hidden class=anchor aria-hidden=true href=#how-is-the-risc-v-isa-organized>#</a></h2><p>In this section we look into how RISC-V is organised</p><h3 id=rv-n-extension-letter>RV N (Extension letter)<a hidden class=anchor aria-hidden=true href=#rv-n-extension-letter>#</a></h3><ul><li>RV stands for RISC-V</li><li>N - Number of bits (Ex: 32 bits)</li><li>Extension letter: This is the Extension for the instruction
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sets (I stands for Integer)</li></ul><h3 id=example-base-isa>Example Base ISA<a hidden class=anchor aria-hidden=true href=#example-base-isa>#</a></h3><p>RV32I, RV64I, RV128I</p><h3 id=standard-extensions>Standard Extensions<a hidden class=anchor aria-hidden=true href=#standard-extensions>#</a></h3><ul><li>M: Math</li><li>A: Atomic</li><li>F: Floating Point</li><li>D: Double Precision Floating Point</li></ul><h4 id=--g-general-purpose-includes-integer-math-atomic-floating-point-and-double-precision-floating-point>- G: General Purpose (Includes, Integer, Math, Atomic, Floating Point and Double Precision Floating Point)<a hidden class=anchor aria-hidden=true href=#--g-general-purpose-includes-integer-math-atomic-floating-point-and-double-precision-floating-point>#</a></h4><h3 id=linux-supports>Linux supports<a hidden class=anchor aria-hidden=true href=#linux-supports>#</a></h3><h4 id=rv64g>RV64G<a hidden class=anchor aria-hidden=true href=#rv64g>#</a></h4><p>This is called as RISC-V 64 bit General Purpose</p><h2 id=lets-talk-a-bit-indepth-of-rv32i>Lets talk a bit indepth of RV32I<a hidden class=anchor aria-hidden=true href=#lets-talk-a-bit-indepth-of-rv32i>#</a></h2><p>RV32I is a base ISA and the easiest to understand.
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RV32I means it’s RISC-V 32 bit Integer ISA.</p><pre tabindex=0><code>Registers: x0-x31
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(x0 is hardwired to 0)
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</code></pre><p>Each register is 32 bits which can be called as 1 word.</p><p><img loading=lazy src=https://raw.githubusercontent.com/Artoriuz/RV32I-SC/master/images/schematic.png>
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Fig 1.0 <a href=https://github.com/Artoriuz/RV32I-SC>Simplified schematics of RV32I</a></p><p>Now we will recall the basics and try to understand
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how to read an instruction.</p><pre tabindex=0><code>add rd,rs1,rs2
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</code></pre><ul><li>add: is the opcode</li><li>rd: is the destination register</li><li>rs1: Source register 1</li><li>rs2: Source register 2</li></ul><p><img loading=lazy src=/img/rv32i.png>
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Fig 1.1 <a href=https://github.com/jameslzhu/riscv-card/blob/master/riscv-card.pdf>Assembly instructions for RV32I</a></p><p><img loading=lazy src=/img/registersrv32i.png>
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Fig 1.2 <a href=https://github.com/jameslzhu/riscv-card/blob/master/riscv-card.pdf>Registers for RV32I</a></p><h2 id=interesting-research-papers>Interesting research papers<a hidden class=anchor aria-hidden=true href=#interesting-research-papers>#</a></h2><ul><li><p><a href=https://ieeexplore.ieee.org/document/8564810>Implementing RISC-V System-on-Chip for Acceleration of Convolution Operation and Activation Function Based on FPGA (Field programmable gate arrays)</a>: FGPA are mostly for application specific integrated circuits. An example would be Intel using FGPA to
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prototype new chips. The objective of the paper was to design
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a RISC-V processor for specific tasks such as Convolution functions and activation functions. The result was that the
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RISC-V processor was faster than CPU + co-processor mode and
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used lesser than the CPU + GPU mode.</p></li><li><p><a href=https://edge.seas.harvard.edu/files/edge/files/carrv_workshop_submission_2019_camera_ready.pdf>Towards deep learning using Tensorflow lite on RISC-V</a>: This paper focuses on ISA extensions customized for
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machine learning kernels. The software infrastructure implemented was optimized for neural network execution.
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The following was integrated into Tensorflow lite. The
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result was that instructions was reduced by 8X.</p></li><li><p><a href="https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9191411">A compiler comparison in the RISC-V ecosystem</a>: Comparing LLVM and GCC performance on RISC-V. LLVM and GCC
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produce same binary size but both have different execution
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times.</p></li></ul><h2 id=interesting-open-source-projects>Interesting Open Source projects<a hidden class=anchor aria-hidden=true href=#interesting-open-source-projects>#</a></h2><ul><li><a href=https://github.com/Wren6991/RISCBoy>RISCBoy</a>: It is an open-source portable games console, designed from scratch.
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RISC-V compatible CPU. Has raster graphics pipelines and display controllers. It consists of other infrastructure such as memory
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controllers and GPIO ports. It also consists of a CAD design of
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the PCB layout.</li><li><a href=https://github.com/skordal/potato>Potato</a>: The Potato Processor is a simple RISC-V processor written in VHDL for use in FPGAs. It implements the 32-bit integer subset of the RISC-V Specification version 2.0.</li><li><a href=https://github.com/vmmc2/Vulcan>Vulcan</a>: RISC-V instruction set simulation built for education using flutter.</li></ul></div><footer class=post-footer><ul class=post-tags><li><a href=http://localhost:1313/tags/riscv/>RISCV</a></li><li><a href=http://localhost:1313/tags/open-source/>Open Source</a></li></ul><nav class=paginav><a class=prev href=http://localhost:1313/technicalposts/p2prc-1.0.0-alpha-release/><span class=title>« Prev</span><br><span>Alpha Release P2PRC v1.0.0</span>
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