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Akilan Selvacoumar
2025-07-27 21:08:47 +01:00
parent 4ec5e6da4c
commit 9743fa8567
16 changed files with 393 additions and 336 deletions
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docs/EuroSys/Paper/paper.aux
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docs/EuroSys/Paper/paper.bbl
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@@ -246,16 +246,28 @@
% addressing, we introduce a memory allocator that can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that
% our allocator can reduce TLB misses by up to 90\%, leading to improvements in wall clock runtimes for memory-intensive applications.
The increasing gap between workload memory requirements and the capacity of translation lookaside buffers (TLBs) in hardware cache management of modern processors means that TLB misses
are more frequent, costing additional clock cycles and impacting runtime performance. One solution that has been explored is to use physically contiguous
memory in conjunction with huge pages.
% The increasing gap between workload memory requirements and the capacity of translation lookaside buffers (TLBs) in hardware cache management of modern processors means that TLB misses
% are more frequent, costing additional clock cycles and impacting runtime performance. One solution that has been explored is to use physically contiguous
% memory in conjunction with huge pages.
The contribution is an alternative approach by exploiting capability-based addressing in the
CHERI architecture. This paper presents a new memory allocator called Fat Address Translations (FAT) which associates capabilities with memory pointers by integrating
block-based allocations within huge pages. When the FAT allocator is ran independently and embedded inside Jemalloc, it reduces by up to 99\% walking the TLB hierarchy. This leads to
decreasing runtimes for memory read and write intensive applications.
% The contribution is an alternative approach by exploiting capability-based addressing in the
% CHERI architecture. This paper presents a new memory allocator called Fat Address Translations (FAT) which associates capabilities with memory pointers by integrating
% block-based allocations within huge pages. When the FAT allocator is ran independently and embedded inside Jemalloc, it reduces by up to 99\% walking the TLB hierarchy. This leads to
% decreasing runtimes for memory read and write intensive applications.
% The FAT allocator when ran independently and embedded inside Jemalloc reduces walking the TLB hierarchy by upto 90\%, which leads to decreasing runtimes
% for memory read and write intensive applications.
The widening gap between application memory demands and the limited capacity of hardware Translation Lookaside Buffers (TLBs)
in modern processors leads to frequent TLB misses, incurring significant performance penalties due to additional clock cycles
spent on page table walks. A common mitigation strategy involves the use of physically contiguous memory and huge pages to
reduce TLB pressure.
This paper introduces a solution that leverages capability-based addressing in the CHERI architecture with huge pages.
We present Fat Address Translations (FAT), a memory allocator that embeds allocation metadata directly within
pointer capabilities and manages memory in block-based allocations within huge pages. By encoding allocation bounds in capabilities,
FAT enables more efficient pointer dereferencing and reduces reliance on smaller page table entry lookups. Our evaluation shows that FAT,
both as a standalone allocator and when integrated into Jemalloc, reduces TLB hierarchy walks by up to 99\% in contrast to standard system allocators and improves runtime performance for memory read intensive applications.
This demonstrates that capability-based addressing can repurposed to mitigate TLB pressure.
\end{abstract}
%%
@@ -338,7 +350,8 @@
% accelerating memory management operations.
In computing, achieving high performance is an ongoing challenge, especially as
applications handle increasingly memory intensive workloads. Performance referring to memory access rather than compute bound.
modern applications handle increasingly memory intensive workloads.
% Performance referring to memory access rather than compute bound.
Memory management is a key factor in reducing the time it takes to access a memory region.
A Translation Lookaside Buffer (TLB) is a specialised cache in the memory management unit (MMU).
It reduces the time required to convert virtual addresses to physical addresses. When a program accesses
@@ -353,11 +366,11 @@ To tackle this issue, researchers have explored new solutions, including the use
huge pages~\cite{panwar_hawkeye_2019}.
Huge pages also known as large pages allow for the allocation of memory in significantly larger chunks
compared to traditional small pages by reducing the number of TLB entries needed to access a given amount
compared to traditional small pages which leads to fewer number of TLB entries needed to access a given amount
of memory. Huge pages offer a potential avenue for optimising TLBs which are used by reducing the number
of entries needed to map large memory regions. This not only decreases the frequency of
TLB misses but also lowers the overhead associated with address translation and therefore minimising
these bottlenecks.
TLB misses but also lowers the overhead associated with address translation in regards to traversing the TLB cache
hierarchy and therefore minimising these bottlenecks.
% huge pages can improve system performance in aspects such as speeding
% up memory-intensive applications, reducing latency in data access and enhancing throughput for
% workloads that rely heavily on large datasets.
@@ -368,9 +381,9 @@ these bottlenecks.
% Answer: The focus on this paper is on single core execution.
Simultaneously, advancements in hardware-level security, such as the Capability Hardware Enhanced RISC Instructions (CHERI)
~\cite{woodruff_cheri_2014} which are pointers that are replaced with capabilities with 128-bit or 256-bit
~\cite{woodruff_cheri_2014} which are standard 64-bit pointers that are replaced with capabilities with 128-bit or 256-bit
encoding scheme which consists of both the address and metadata. The metadata includes bounds, permissions and validity of the pointer
which forms a capability. This transformation enforces strict memory
which forms a capability. This transformation of larger pointers enforces strict memory
safety as capabilities prevent arbitrary pointer arithmetic and unauthorised memory access.
CHERI's capability-based addressing approach not
only strengthens system security by tightly controlling memory access but also opens avenues for optimising memory management
@@ -387,7 +400,7 @@ memory allocations by emulating block allocations on physically contiguous memor
used to optimise memory allocation by encoding memory bounds directly within pointers, reducing TLB reliance
(Section ~\ref{sec:128bitCompressedBounds}).
\item \textbf{Memory Allocation Algorithms (FAT allocator)}: Provides an algorithm for allocating, freeing
\item \textbf{Memory Allocation Algorithms (FAT allocator)}: Presents an algorithm for allocating, freeing
physically contiguous memory , and integrating huge pages with CHERI's capability-based bounds for enhanced memory management
(Section ~\ref{sec:MemoryAllocator}).
@@ -519,7 +532,8 @@ bound encoding technique with an internal exponent mechanism that offers greater
\label{sec:FatPointerTranslations}
Fat Address Translations (FAT) is our new memory allocator for CHERI. It uses the CHERI architecture to
bring about block-based allocations in physically contiguous memory.
FAT leverages techniques like FlexPointer~\cite{chen_flexpointer_2023} and RMM~\cite{karakostas_redundant_2015} to
FAT leverages techniques like FlexPointer~\cite{chen_flexpointer_2023}, RMM~\cite{karakostas_redundant_2015} in context of introducing
a range table to store custom address translation memory ranges to
reduce pressure on the TLB. A key component
in this implementation is the use of range addresses with CHERI CC~\cite{woodruff_cheri_2019}.
@@ -671,7 +685,7 @@ representation of bounds within CHERI CC.
Instead of relying on fixed-size TLB entries with set page sizes (such as 4KB, 2MB, or 1GB), FAT uses CHERI
CC to define dynamic bounds based on the size requested at allocation time (e.g., during a \textit{malloc} call).
This approach offers a more flexible alternative to the traditional fixed-size TLB model.
This approach offers flexible translation entry sizes compared to the traditional fixed-size TLB model.
This means that the default behavior of most allocators, such
as Jemalloc, would allow precise representation of bounds within
@@ -739,7 +753,7 @@ to track and access memory within physically contiguous memory.
\section{Memory allocator design}
\label{sec:MemoryAllocator}
This section presents a straightforward memory allocator design which is implemented based on the
This section presents a memory allocator design which is implemented based on the
principles outlined in FAT (Section ~\ref{sec:FatPointerTranslations}). The allocator consists of three core functions: \textit{InitAlloc},
\textit{malloc}, and \textit{free}. The \textit{InitAlloc} function initialises the memory pool, setting up the necessary
data structures and metadata required for efficient memory management. The \textit{malloc} function is
@@ -774,7 +788,7 @@ itself. The start and end addresses correspond to the size of the memory block r
approach introduces a method of memory tracking, where the bounds of the allocated region is
explicitly encoded in the address which enables efficient monitoring and management of memory usage.
Furthermore, this design uses shared huge page TLB entries to map
Furthermore, this design uses huge page TLB entries to map
and track memory addresses. By encoding bounds directly into the address, the algorithm ensures that memory
accesses remain within the allocated region. Thereby reducing the risk of out-of-bounds
errors. This use of FAT and shared TLB entries not only align with the principles of
@@ -890,7 +904,7 @@ for munmap the \textit{free} function (Algorithm \ref{alg:free}).
\subsection{Mmap replaced with MALLOC}
The os\_pages\_map function (Algorithm~\ref{alg:JemallocMalloc}) simulates jemalloc's low-level page
The os\_pages\_map function (Algorithm~\ref{alg:JemallocMalloc}) simulates Jemalloc's low-level page
mapping routine. It first checks if a specific address is
requested in case relevant to CheriABI~\cite{CheriABI} where such behavior
is disallowed and returns NULL. It then allocates memory using the custom MALLOC(size) (Algorithm~\ref{alg:malloc}) function and validates
@@ -899,10 +913,10 @@ if one was provided. If there's a mismatch, it unmaps calling FREE() (Algorithm~
memory and returns NULL; otherwise, it returns the allocated
pointer.
This approach mentioned above is embedded inside jemalloc's strategy of managing memory through arenas and size classes.
In jemalloc, memory is divided into chunks, which are further subdivided into runs and regions to
This approach mentioned above is embedded inside Jemalloc's strategy of managing memory through arenas~\cite{jemalloc} and size~\cite{jemalloc} classes.
In Jemalloc, memory is divided into chunks, which are further subdivided into runs and regions to
handle allocations of various sizes efficiently. By aligning sizes and managing allocations within
predefined structures, jemalloc minimizes fragmentation~\cite{evans_scalable_nodate}.
predefined structures, Jemalloc minimizes fragmentation~\cite{evans_scalable_nodate}.
% The only function required to be replaced with Malloc was os\_pages\_map,
% pages\_map and pages\_commit\_impl as show in
@@ -923,9 +937,9 @@ predefined structures, jemalloc minimizes fragmentation~\cite{evans_scalable_nod
\subsection{Munmap replaced with FREE}
The os\_pages\_unmap (Algorithm~\ref{alg:JemallocFree}) represents a customized abstraction of jemallocs
The os\_pages\_unmap (Algorithm~\ref{alg:JemallocFree}) represents a customized abstraction of Jemallocs
memory unmapping routine, designed to integrate with the previously defined simplified
free(ptr) implementation. In conventional jemalloc configurations, os\_pages\_unmap would
free(ptr) implementation. In conventional Jemalloc configurations, os\_pages\_unmap would
invoke low-level system calls such as munmap to release virtual memory pages back to the
operating system. However, in this adapted version, the function instead delegates the
deallocation to a higher-level FREE(addr) (Algorithm~\ref{alg:free}).
@@ -933,12 +947,12 @@ deallocation to a higher-level FREE(addr) (Algorithm~\ref{alg:free}).
The function begins by enforcing two invariants through assertions: first, that the input
address addr is aligned to the operating system's page size and second that
the size of the memory region is also a multiple of os\_page. These alignment checks are
critical for maintaining consistency with jemalloc's internal page-based memory
critical for maintaining consistency with Jemalloc's internal page-based memory
management semantics and ensuring compatibility with the allocator's expectations.
Following these checks the memory at the specified address is deallocated via the
FREE(addr) (Algorithm~\ref{alg:free}) operation.
The following changes done to free is embedded inside jemalloc's deallocation mechanism,
The following changes done to free is embedded inside Jemalloc's deallocation mechanism,
where metadata associated with each allocation
(such as size and location) is used to efficiently return memory to the appropriate
arena or pool. Jemalloc maintains
@@ -1012,7 +1026,7 @@ failing to overwrite the C program at runtime with the intended \textit{malloc}
The second allocator was the standard OS memory allocator, which in the case of
CHERIBSD is Jemalloc.
Performance measurements (table ~\ref{table:ARMPerf}) were carried out using ARM performance counters~\cite{PerformanceCounter} to
Performance measurements (table ~\ref{table:ARMPerf}) were carried out using ARM hardware performance counters~\cite{PerformanceCounter} to
ensure accurate evaluation. These counters provided detailed metrics allowing
us to compare the performance of the two allocators and assess the impact of
the proposed changes.
@@ -1041,13 +1055,6 @@ the proposed changes.
& due to a translation table walk \\
& or accessing another level of TLB cache. \\
& \\
(p/cpu\_cycles) CPU cycles & The CPU CYCLES counter increases with \\
& every clock cycle. However, it can be \\
& affected by changes in clock frequency, \\
& such as when WFI (Wait for Interrupt) \\
& or WFE (Wait for Event) \\
& instructions pause the clock. \\
& \\
(p/dtlb\_walk) Data TLB walks & Data TLB access with at least \\
& one translation table walk. \\
& \\
@@ -1157,25 +1164,12 @@ This extension is described by Holt and Singh ~\cite{holt1995}.
\begin{figure*}
\begin{multicols}{2}
\begin{subfigure}{\linewidth}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-dtlb-walk.png}
\caption{DTLB Walks}
\label{fig:dtlb-walk}
\end{subfigure}\par
\begin{subfigure}{\linewidth}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-l1tlb-reads.png}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/large/bargraph-large-l1_tlb_rd.png}
\caption{L1 TLB Reads}
\label{fig:l1tlb-reads}
\end{subfigure}\par
\end{multicols}
\begin{multicols}{2}
\begin{subfigure}{\linewidth}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-l1tlb-refill.png}
\caption{L1 TLB Refill}
\label{fig:l1tlb-refill}
\end{subfigure}\par
\begin{subfigure}{\linewidth}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-l2tlb-reads.png}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/large/bargraph-large-l2_tlb_rd.png}
\caption{L2 TLB Reads}
\label{fig:l2tlb-reads}
\end{subfigure}\par
@@ -1183,12 +1177,25 @@ This extension is described by Holt and Singh ~\cite{holt1995}.
\begin{multicols}{2}
\begin{subfigure}{\linewidth}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-ll-cache-rd.png}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/large/bargraph-large-dtlb_walk.png}
\caption{DTLB Walks}
\label{fig:dtlb-walk}
\end{subfigure}\par
\begin{subfigure}{\linewidth}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/large/bargraph-large-l1tlb_refill.png}
\caption{L1 DTLB Refill}
\label{fig:l1tlb-refill}
\end{subfigure}\par
\end{multicols}
\begin{multicols}{2}
\begin{subfigure}{\linewidth}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/large/bargraph-large-llcache.png}
\caption{LL Cache Reads}
\label{fig:ll-cache-rd}
\end{subfigure}\par
\begin{subfigure}{\linewidth}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-wallclock.png}
\includegraphics[width=\linewidth]{diagram/benchmarks-group/large/bargraph-large-wallclock.png}
\caption{Wall Clock Time}
\label{fig:wallclock}
\end{subfigure}\par
@@ -1207,7 +1214,7 @@ This extension is described by Holt and Singh ~\cite{holt1995}.
% \caption{\label{fig:bargrapwh}Percentage difference between the modified memory allocator against the default system memory allocator}
% \end{figure*}
Figure \ref{fig:benchmarks-group} highlights the performance comparison between the modified memory allocator and
Figure~\ref{fig:benchmarks-group} highlights the performance comparison between the modified memory allocator and
Jemalloc, the default memory allocator. The FAT memory allocator is specifically optimised
for use with huge pages and demonstrates a clear advantage in scenarios where memory allocation
patterns benefit from its design. The results align with expectations, showcasing the impact
@@ -1225,7 +1232,7 @@ of its capability to handle memory more efficiently by leveraging huge pages.
% FAT allocator embedded inside Jemalloc. These results suggest that FAT allocator embedded inside Jemalloc may arrange memory
% in a manner that enhances spatial locality at the page level, particularly for workloads like Memaccess and Glibc.
\item L1 TLB reads: L1 TLB reads are critical for achieving fast memory access; therefore, a
\item L1 TLB reads (Figure~\ref{fig:l1tlb-reads}): L1 TLB reads are critical for achieving fast memory access; therefore, a
reduction in events that could signify misses or lead to further lookups is generally beneficial.
In the Kmeans benchmark, the FAT allocator demonstrated 13\% fewer L1 TLB reads than the baseline allocator.
However, when the FAT allocator was embedded within Jemalloc, the L1 TLB reads were the same as the baseline.
@@ -1234,7 +1241,7 @@ of its capability to handle memory more efficiently by leveraging huge pages.
there was no difference for either allocator. For the Barnes benchmark, the FAT allocator exhibited 5\%
fewer L1 TLB reads, and the result was the same for the FAT allocator embedded within Jemalloc.
\item L2 TLB reads: L2 Data TLB reads (or lookups) serve as a secondary cache for address translations.
\item L2 TLB reads (Figure~\ref{fig:l2tlb-reads}): L2 Data TLB reads (or lookups) serve as a secondary cache for address translations.
FAT allocator consistently performed at 98\% lesser L2 TLB reads for this metric across all benchmarks except Barnes
which was 4\% lesser. FAT allocator embedded inside Jemalloc also showed significant change for Kmeans, Memaccess, and Richards. However, for the Glibc benchmark
it achieved a reduction of 60\% in L2 TLB reads. This mirrors its L1D TLB improvement for Glibc and suggests that its
@@ -1242,7 +1249,7 @@ of its capability to handle memory more efficiently by leveraging huge pages.
Glibc's high frequency of malloc calls that stress memory management. A minor reduction of 5 \% was also observed for the Barnes
benchmark with FAT allocator embedded inside Jemalloc.
\item DTLB walks: which occur when a virtual-to-physical
\item DTLB walks (Figure~\ref{fig:dtlb-walk}): which occur when a virtual-to-physical
address translation is not found in the DTLB and a page table traversal is necessary, represent a performance
cost. thus, fewer walks are preferable. In the observed tests neither FAT allocator nor FAT allocator embedded inside Jemalloc
demonstrated significant deviation from the baseline performance of 99\% lesser walks.
@@ -1253,7 +1260,7 @@ of its capability to handle memory more efficiently by leveraging huge pages.
% of DTLB misses that necessitate page table walks within these specific workloads. Even for the Memaccess benchmark,
% which is designed with random list traversals that can stress TLB pressure, the impact on dTLB walks was negligible according to the provided graphs.
\item L1 TLB refills: L1 Data TLB refills are a direct consequence of L1 TLB misses; therefore, fewer refills
\item L1 TLB refills (Figure~\ref{fig:l1tlb-refill}): L1 Data TLB refills are a direct consequence of L1 TLB misses; therefore, fewer refills
indicate better performance. Interestingly, despite the variations observed in L1 TLB reads for the FAT allocator
embedded within Jemalloc, the L1 TLB refills metric showed a significant reduction of 99\% for both the standalone
FAT allocator and the FAT allocator embedded within Jemalloc. This consistent and substantial improvement over the baseline was observed across all tested benchmarks: Kmeans, Memaccess, Glibc, Richards, and Barnes.
@@ -1266,12 +1273,12 @@ of its capability to handle memory more efficiently by leveraging huge pages.
% events than solely those leading to refills, or perhaps the absolute number of critical misses resulting in refills was minimal to begin with and thus
% not significantly affected by the allocators in these tests.
\item Last-level cache: Cache read misses in the Last-Level Cache (LLC) are critical performance indicators, as they typically lead to
\item Last-level cache (Figure~\ref{fig:ll-cache-rd}): Cache read misses in the Last-Level Cache (LLC) are critical performance indicators, as they typically lead to
slower data retrievals from main memory. Consequently, a lower number of misses is highly desirable. The performance on this
metric varied considerably across both allocators and benchmarks. The FAT allocator exhibited the highest variance in the
kmeans benchmark, achieving 57\% fewer cache misses compared to the baseline allocator. In contrast, it recorded 18\% more
misses in memaccess, 65\% fewer in glibc, 31\% more in Richards, and 18\% more in barnes.
When the FAT allocator was embedded within jemalloc, the results shifted notably: kmeans experienced 19\% more misses
When the FAT allocator was embedded within Jemalloc, the results shifted notably: kmeans experienced 19\% more misses
relative to the baseline, memaccess saw a substantial 77\% reduction, while glibc incurred a dramatic 370\% increase particularly
significant given its malloc intensive nature. There was no change in LLC misses for Richards, whereas barnes suffered from 68\%
more misses.
@@ -1292,11 +1299,11 @@ of its capability to handle memory more efficiently by leveraging huge pages.
% This high variability indicates that memory placement strategies of the allocators interact diversely with the specific access patterns of each benchmark,
% such as the difference between the large data arrays in K-Means versus the linked structures common in Memaccess or Richards.
\item Wall clock: Wallclock time serves as the definitive metric for evaluating overall execution performance.
\item Wall clock (Figure~\ref{fig:wallclock}): Wallclock time serves as the definitive metric for evaluating overall execution performance.
When using the FAT allocator, glibc demonstrated the most significant improvement, with a 51\% reduction in wallclock
runtime compared to the baseline allocator. This was followed by memaccess with a 34\% decrease, barnes with a 4\% reduction,
and kmeans with a modest 1.8\% improvement. Conversely, Richards exhibited a slight increase of 1\% in runtime.
When the FAT allocator was integrated into jemalloc, the performance impact varied. Glibc experienced a 16.2\% increase
When the FAT allocator was integrated into Jemalloc, the performance impact varied. Glibc experienced a 16.2\% increase
in wallclock time, while barnes showed a 7\% rise. Both Richards and kmeans maintained the same runtime as the baseline
allocator, whereas memaccess recorded a 4\% reduction.
@@ -1412,21 +1419,51 @@ bottlenecked by factors such as computation or I/O rather than memory translatio
% This modification reduces the dependency on the TLB, decreasing latency and improving performance, especially for frequent memory operations.
\section{Conclusion} %Title of the Conclusion
This paper addresses the growing disparity between application workloads and the capacity of TLBs.
To mitigate this gap, FAT proposed leveraging physically contiguous memory with CHERI bounds to reduce TLB walks.
FAT is a memory allocator that uses huge pages with the CHERI CC scheme to track allocations within the
allocated huge page. This approach reduces the number of TLB entries needed while using bounds
to minimise fragmentation.
This paper has presented FAT, a memory allocator
designed to address the growing mismatch between application memory demands and
the limited reach of TLBs in modern processors.
By leveraging physically contiguous memory through huge pages and embedding
allocation metadata within CHERI's compressed capability based pointers,
FAT significantly reduces the overhead associated with virtual-to-physical
address translation.
\newline
FAT achieves block-based allocation within huge pages, enabling memory tracking
without relying heavily on traditional page table mechanisms. Benchmark evaluations
demonstrate that FAT can reduce TLB walks by up to 99\%, resulting in substantial
performance improvements in memory-intensive workloads. When applied to
microbenchmarks, FAT reduced wall-clock runtime by up to 51\% for Glibc and
34\% for Memaccess, while also achieving up to 68\% fewer L1 TLB reads and 98\%
fewer L2 TLB reads. In contrast, macro benchmarks such as Kmeans and Barnes
showed more modest gains of 1.8\% and 4\% in runtime, respectively, reflecting
the allocator's limited impact in compute-bound scenarios.
\newline
Although performance gains are less significant for larger or computation-heavy applications,
the results underscore the allocator's potential to enhance memory management in
high-throughput environments. More broadly, this work demonstrates how
capability based architectures originally designed to ensure memory safety can
be effectively repurposed to optimise address translation.
FAT thus represents a promising direction for developing more scalable
and efficient memory allocation strategies in systems adopting
capability aware architectures.
% This paper addresses the growing disparity between application workloads and the capacity of TLBs.
% To mitigate this gap, FAT proposed leveraging physically contiguous memory with CHERI bounds to reduce TLB walks.
% FAT is a memory allocator that uses huge pages with the CHERI CC scheme to track allocations within the
% allocated huge page.
% This approach reduces the number of TLB entries needed while using bounds
% to minimise fragmentation.
% Additionally,
% the report explores advancements in system security, particularly through the Capability Hardware Enhanced RISC Instructions (CHERI)
% architecture. CHERI's capability-based addressing enhances system security by associating capabilities with memory pointers,
% restricting access to memory regions, and thus protecting against various security threats. Importantly, these mechanisms
% can also improve the reduction of TLB walks to memory allocators by using CHERI bounds while maintaining CHERI's security guarantees.
\newline
The benchmarks demonstrates the FAT allocator and the FAT allocator embedded within Jemalloc which reduces the TLB misses by upto 90\%,
leading to substantial performance gains in memory-intensive workloads, though the improvements are less pronounced
for larger and computation-heavy applications. These results highlight the allocators potential to advance memory management
by repurposing CHERI's capability-based model with the use of huge pages.
% \newline
% The benchmarks demonstrates the FAT allocator and the FAT allocator embedded within Jemalloc which reduces the TLB walks by upto 99\%,
% leading to substantial performance gains in memory-intensive workloads, though the improvements are less pronounced
% for larger and computation-heavy applications. These results highlight the allocators potential to advance memory management
% by repurposing CHERI's capability-based model with the use of huge pages.