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added corrections to the abstract, FAT pointer section and conclusion

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Akilan Selvacoumar
2025-04-04 14:20:56 +01:00
parent 05cb379c0c
commit a0d0ae6ec9
9 changed files with 339 additions and 290 deletions
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61
docs/EuroSys/Paper/paper.aux
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5
docs/EuroSys/Paper/paper.bbl
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@@ -58,6 +58,11 @@ Dongwei Chen, Dong Tong, Chun Yang, Jiangfang Yi, and Xu~Cheng.
tagged pointers.
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Gokul~B. Kandiraju and Anand Sivasubramaniam.
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\newblock {\em SIGMETRICS Perform. Eval. Rev.}, 30(1):129–139, June 2002.
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{JEMALLOC}.

56
docs/EuroSys/Paper/paper.blg
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@@ -210,26 +210,33 @@
%% The abstract is a short summary of the work to be presented in the
%% article.
\begin{abstract}
The increasing disparity between application workloads and the capacity of s (TLB)
has prompted researchers to explore innovative solutions to mitigate this gap. One such approach involves
leveraging physically contiguous memory and the use of huge pages to optimize TLB utilization. Huge pages,
which group multiple smaller pages into larger ones, reduce TLB miss rates by decreasing the number of entries
required in the TLB, thus improving overall performance. Concurrently, advancements in hardware-level system
security, exemplified by the Capability Hardware Enhanced RISC Instructions (CHERI) architecture, offer
additional opportunities for improving memory management and security.
% The increasing disparity between application workloads and the capacity of s (TLB)
% has prompted researchers to explore innovative solutions to mitigate this gap. One such approach involves
% leveraging physically contiguous memory and the use of huge pages to optimize TLB utilization. Huge pages,
% which group multiple smaller pages into larger ones, reduce TLB miss rates by decreasing the number of entries
% required in the TLB, thus improving overall performance. Concurrently, advancements in hardware-level system
% security, exemplified by the Capability Hardware Enhanced RISC Instructions (CHERI) architecture, offer
% additional opportunities for improving memory management and security.
CHERI introduces capability-based addressing, a novel approach that enhances system security by
associating capabilities with memory pointers. These capabilities restrict access to memory regions,
thereby fortifying the system against various security threats. Importantly, the mechanisms implemented in
CHERI for enforcing memory protection can also serve as accelerators for standard user-space memory allocators.
By leveraging capability-based addressing, memory allocators can efficiently manage memory resources, ensure
robust security measures are in place, and potentially enhance performance through the integration of huge pages,
further improving TLB efficiency and memory handling.
% CHERI introduces capability-based addressing, a novel approach that enhances system security by
% associating capabilities with memory pointers. These capabilities restrict access to memory regions,
% thereby fortifying the system against various security threats. Importantly, the mechanisms implemented in
% CHERI for enforcing memory protection can also serve as accelerators for standard user-space memory allocators.
% By leveraging capability-based addressing, memory allocators can efficiently manage memory resources, ensure
% robust security measures are in place, and potentially enhance performance through the integration of huge pages,
% further improving TLB efficiency and memory handling.
Through our evaluation using both micro and macro benchmarks,
we show that our allocator can reduce TLB misses by up to 90\%,
leading to substantial improvements in wall clock runtimes for memory-intensive
applications.
% Through our evaluation using both micro and macro benchmarks,
% we show that our allocator can reduce TLB misses by up to 90\%,
% leading to substantial improvements in wall clock runtimes for memory-intensive
% applications.
The increasing disparity between application workloads and the capacity of translation lookaside buffers (TLBs) has prompted researchers
to explore solutions to mitigate the extra clock cycles incurred during a TLB miss. One such approach involves leveraging physically contiguous memory
and the use of huge pages. Concurrently, advancements in hardware-level system security—exemplified by the Capability Hardware
Enhanced RISC Instructions (CHERI) architecture—offer additional opportunities for improving TLB performance. CHERI introduces
capability-based addressing, a novel approach that enhances system security by associating capabilities with memory pointers. By leveraging capability-based
addressing, memory allocators can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that
our allocator can reduce TLB misses by up to 90\%, leading to improvements in wall clock runtimes for memory-intensive applications.
\end{abstract}
%%
@@ -498,19 +505,19 @@ number of TLB entries required.
\caption{Range of memory}
\label{fig:RangeOfMemory}
\end{figure}
Integrating range bounds directly into FAT-pointers enables the CHERI architecture
to enforce memory access restrictions at the pointer level thus allowing
tracking of memory ranges on a pointer level. In this implementation, memory ranges are established using
% Integrating range bounds directly into FAT-pointers enables the CHERI architecture
% to enforce memory access restrictions at the pointer level thus allowing
% tracking of memory ranges on a pointer level.
In this implementation, memory ranges are established using
bounds encoded within the FAT-pointer, adhering to the CHERI
128-bit bounds compression scheme~\cite{woodruff_cheri_2019}.
CHERI 128-bit bounds compression scheme~\cite{woodruff_cheri_2019}.
Figure \ref{fig:RangeOfMemory} illustrates a straightforward use-case in which the dark pink line represents a single,
large contiguous memory area, or huge page. Within this huge page, the orange and blue lines indicate
two separate memory allocations equivalent to invoking malloc twice to allocate memory in distinct regions.
This scenario simulates a block-based memory allocator operating within the confines of the huge page.
The allocations use the bounds encoded in the FAT-pointer, ensuring tracking of the allocated memory regions.
By using the FAT-pointer bounds, this method maintains the
integrity and contiguity of the allocated blocks within the huge page.
By using the CHERI bounds, this method maintains the contiguity of the allocated blocks within the huge page.
\subsection{128 bit compressed bounds}
\label{sec:128bitCompressedBounds}
@@ -538,12 +545,14 @@ eliminating the need for multiple TLB entries for each allocation.
One key analysis of CHERI CC highlights that allocators like Jemalloc typically allocate objects under
512 bytes. When an object’s bounds cannot be precisely represented, padding is required to ensure
memory safety. However, it has been observed that Jemalloc rarely needs more than 6 bits to store the
memory safety. However, it has been observed that Jemalloc rarely needs more than 6 bits~\cite{woodruff_cheri_2019} to store the
exponent values within compressed bounds.
This means that the default behavior of most allocators, such as Jemalloc, would allow precise
representation of bounds within a FAT-pointer. These pointers can then be repurposed as memory ranges
in custom memory allocators, offering a more flexible alternative to fixed-size TLB entries.
This means that the default behavior of allocators such as Jemalloc, would allow precise
representation of bounds within CHERI CC. With our implementation rather than using
fixed size TLB entries we use the CHERI CC bounds to be repurposed to encode dynamic sized addresses ranges.
% These pointers can then be repurposed as memory ranges
% in custom memory allocators, offering a more flexible alternative to fixed-size TLB entries.
% \subsection{Creation of Physically Contiguous Memory Ranges}
@@ -562,18 +571,19 @@ Traditional address translation methods rely on hierarchical
structures to map virtual addresses to physical addresses.
This often requires multiple entries to handle different
memory segments, which increases overhead and adds complexity
to the translation process. In contrast, Our approach
to the translation process~\cite{TLBBehavoir}. In contrast, Our approach
simplifies this by using a single TLB
entry to translate multiple addresses within a contiguous memory
range. This reduces the number of TLB entries needed, making the
translation process more efficient and less complex.
By consolidating address translations into a single TLB entry,
this method cuts down on the overhead of managing many entries.
the FAT Based Address cuts down on the overhead of managing many entries.
It also takes advantage of the bounds encoded within fat-pointers
to track and access memory more efficiently. This streamlined
approach allows for precise and effective memory management,
especially within large, contiguous memory regions like huge pages.
to track and access memory.
% This streamlined (TODO)
% approach allows for precise and effective memory management,
% especially within large, contiguous memory regions like huge pages.
Overall, it simplifies memory operations while improving performance
and reduces TLB overhead by reducing TLB walks.
@@ -593,12 +603,12 @@ data structures and metadata required for efficient memory management. The mallo
responsible for allocating a contiguous block of memory of a specified size, while the free
function deallocates the memory, returning it to the pool for future use.
A notable feature of this malloc implementation is its compatibility with kernel modules,
where it can be integrated as an alternative to the mmap system call. This integration
ensures that memory allocations are physically contiguous. By providing physically contiguous
memory blocks, this allocator can serve as a foundational layer for standard block-based allocators,
such as Jemalloc, enabling them to operate with significantly lesser L1 TLB misses with programs with heavy memory usage with smaller allocations where physical memory
contiguity is essential.
% A notable feature of this malloc implementation is its compatibility with kernel modules,
% where it can be integrated as an alternative to the mmap system call. This integration
% ensures that memory allocations are physically contiguous. By providing physically contiguous
% memory blocks, this allocator can serve as a foundational layer for standard block-based allocators,
% such as Jemalloc, enabling them to operate with significantly lesser L1 TLB misses with programs with heavy memory usage with smaller allocations where physical memory
% contiguity is essential.
\begin{algorithm}
\caption{Malloc implementation}
@@ -646,8 +656,9 @@ efficient memory management but also demonstrates a practical usecase of huge pa
the corresponding memory region from the address space, ensuring efficient and accurate memory management.
By extracting the bounds and size directly from the FAT-pointer, the free function eliminates the need
for additional metadata lookups or complex data structures, streamlining the deallocation process.
This approach not only enhances performance but also reduces the risk of memory leaks or fragmentation.
for additional metadata lookups or complex data structures.
% , streamlining the deallocation process.
% This approach not only enhances performance but also reduces the risk of memory leaks or fragmentation.
@@ -857,7 +868,7 @@ bottlenecked by factors such as computation or I/O rather than memory translatio
\centering
\includegraphics[width=1.1\linewidth]{./diagram/kmeans.png}
\caption{\label{fig:org8683315}Kmeans COZ benchmark executed against various cluster sizes}
\end{figure}
\end{figure}
The K-means algorithm was executed with varying cluster sizes to evaluate the performance difference
between the FAT pointer allocator and the baseline allocator as the workload scales. This analysis
@@ -921,19 +932,23 @@ CHERI capabilities allow pointers to carry metadata about memory bounds, providi
By encoding the offset and bounds within the pointer, the system can directly access memory without needing intermediate translations via the TLB.
This enables the implementation of a block-based allocator that can efficiently manage memory allocations and deallocations within defined bounds.
Bypassing the TLB in RISC-V Tooba.
\subsection{Hardware Modifications:}
The Bluespec design of the RISC-V processor will be modified to allow certain memory operations to bypass the TLB. This means that when a pointer with encoded offset and bounds is used, the system can directly compute the physical address from the capability information.
This modification reduces the dependency on the TLB, decreasing latency and improving performance, especially for frequent memory operations.
\section{Conclusion} %Title of the Conclusion
This paper addresses the growing disparity between application workloads and the capacity of s (TLBs).
To mitigate this gap, it proposes leveraging physically contiguous memory to reduce TLB walks. Additionally,
the report explores advancements in system security, particularly through the Capability Hardware Enhanced RISC Instructions (CHERI)
architecture. CHERI's capability-based addressing enhances system security by associating capabilities with memory pointers,
restricting access to memory regions, and thus protecting against various security threats. Importantly, these mechanisms
can also improve the reduction of TLB walks to memory allocators by using CHERI bounds while maintaining CHERI's security guarantees.
This paper addresses the growing disparity between application workloads and the capacity of TLBs.
To mitigate this gap, we proposed leveraging physically contiguous memory with CHERI bounds to reduce TLB walks.
We designed a memory allocator which uses huge pages with CHERI CC scheme to track allocations within the
allocated huge page. This approach has helped reduce the number of TLB entries needed while using bounds
to minimize fragmentation.
% Additionally,
% the report explores advancements in system security, particularly through the Capability Hardware Enhanced RISC Instructions (CHERI)
% architecture. CHERI's capability-based addressing enhances system security by associating capabilities with memory pointers,
% restricting access to memory regions, and thus protecting against various security threats. Importantly, these mechanisms
% can also improve the reduction of TLB walks to memory allocators by using CHERI bounds while maintaining CHERI's security guarantees.
\newline
Comprehensive benchmarking demonstrates that the allocator reduces TLB misses by up to 90\%,
leading to substantial performance gains in memory-intensive workloads, though the improvements are less pronounced
for larger, computation-heavy applications. These results highlight the allocator's potential to advance memory management

19
docs/EuroSys/Paper/paperReferences.bib
View File

@@ -518,4 +518,23 @@ keywords = {tanslation lookaside buffer, virtual memory}
file = {Arm Architecture Reference Manual for A-profile architecture:/Users/akilan/Zotero/storage/BVZSP7HA/latest.html:text/html},
}
@article{TLBBehavoir,
author = {Kandiraju, Gokul B. and Sivasubramaniam, Anand},
title = {Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks},
year = {2002},
issue_date = {June 2002},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {30},
number = {1},
issn = {0163-5999},
url = {https://doi.org/10.1145/511399.511351},
doi = {10.1145/511399.511351},
abstract = {Despite the numerous optimization and evaluation studies that have been conducted with TLBs over the years, there is still a deficiency in an indepth understanding of TLB characteristics from an application angle. This paper presents a detailed characterization study of the TLB behavior of the SPEC CPU2000 benchmark suite. The contributions of this work are in identifying important application characteristics for TLB studies, quantifying the SPEC2000 application behavior for these characteristics, as well as making pronouncements and suggestions for future research based on these results.Around one-fourth of the SPEC2000 applications (ammp, apsi, galgel, lucas, mcf, twolf and vpr) have significant TLB missrates. Both capacity and associativity are influencing factors on miss-rates, though they do not necessarily go hand-in-hand. Multi-level TLBs are definitely useful for these applications in cutting down access times without significant miss rate degradation. Superpaging to combine TLB entries may not be rewarding for many of these applications. Software management of TLBs in terms of determining what entries to prefetch, what entries to replace, and what entries to pin has a lot of potential to cut down miss rates considerably. Specifically, the potential benefits of prefetching TLB entries is examined, and Distance Prefetching is shown to give good prediction accuracy for these applications.},
journal = {SIGMETRICS Perform. Eval. Rev.},
month = jun,
pages = {129–139},
numpages = {11}
}