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Akilan Selvacoumar
2025-04-03 16:41:26 +01:00
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152
docs/EuroSys/Paper/paper.aux
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42
docs/EuroSys/Paper/paper.bbl
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@@ -28,11 +28,21 @@ Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony Fox, Robert~M.
\newblock {CHERI} concentrate: Practical compressed capabilities.
\newblock 68(10):1455--1469.
\bibitem{chen_flexpointer_2023}
Dongwei Chen, Dong Tong, Chun Yang, Jiangfang Yi, and Xu~Cheng.
\newblock {FlexPointer}: Fast address translation based on range {TLB} and
tagged pointers.
\newblock 20(2):1--24.
\bibitem{THP}
Juan Navarro.
\newblock Practical, transparent operating system support for superpages.
\bibitem{Shadow_superpages}
Cheol~Ho Park and Daeyeon Park.
\newblock Aggressive superpage support with the shadow memory and the
partial-subblock tlb.
\newblock {\em Microprocessors and Microsystems}, 25(7):329--342, 2001.
\bibitem{DirectSegment}
Arkaprava Basu, Jayneel Gandhi, Jichuan Chang, Mark~D. Hill, and Michael~M.
Swift.
\newblock Efficient virtual memory for big memory servers.
\newblock {\em SIGARCH Comput. Archit. News}, 41(3):237–248, June 2013.
\bibitem{karakostas_redundant_2015}
Vasileios Karakostas, Jayneel Gandhi, Furkan Ayar, Adrián Cristal, Mark~D.
@@ -42,6 +52,12 @@ Vasileios Karakostas, Jayneel Gandhi, Furkan Ayar, Adrián Cristal, Mark~D.
\newblock In {\em Proceedings of the 42nd Annual International Symposium on
Computer Architecture}, pages 66--78. {ACM}.
\bibitem{chen_flexpointer_2023}
Dongwei Chen, Dong Tong, Chun Yang, Jiangfang Yi, and Xu~Cheng.
\newblock {FlexPointer}: Fast address translation based on range {TLB} and
tagged pointers.
\newblock 20(2):1--24.
\bibitem{jemalloc}
{JEMALLOC}.
@@ -69,20 +85,4 @@ Arm architecture reference manual for a-profile architecture.
{CHERI}-allocator/benchmarks/benchmarks/{StressTestMalloc}/glibc-bench.c at
main · akilan1999/{CHERI}-allocator.
\bibitem{THP}
Juan Navarro.
\newblock Practical, transparent operating system support for superpages.
\bibitem{Shadow_superpages}
Cheol~Ho Park and Daeyeon Park.
\newblock Aggressive superpage support with the shadow memory and the
partial-subblock tlb.
\newblock {\em Microprocessors and Microsystems}, 25(7):329--342, 2001.
\bibitem{DirectSegment}
Arkaprava Basu, Jayneel Gandhi, Jichuan Chang, Mark~D. Hill, and Michael~M.
Swift.
\newblock Efficient virtual memory for big memory servers.
\newblock {\em SIGARCH Comput. Archit. News}, 41(3):237–248, June 2013.
\end{thebibliography}

8
docs/EuroSys/Paper/paper.blg
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@@ -23,9 +23,9 @@
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@@ -52,7 +52,7 @@
\usepackage{amsmath}
\usepackage{lipsum}
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@@ -108,7 +108,7 @@
%%
%% The majority of ACM publications use numbered citations and
%% references. The command \citestyle{authoryear} switches to the
%% references. The command ~\citestyle{authoryear} switches to the
%% "author year" style.
%%
%% If you are preparing content for an event
@@ -116,7 +116,7 @@
%% citations and references.
%% Uncommenting
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@@ -124,9 +124,9 @@
\begin{document}
%%
%% The "title" command has an optional parameter,
%% The "title" commanSd has an optional parameter,
%% allowing the author to define a "short title" to be used in page headers.
\title{Fat-pointer Address Translations}
\title{Fat Address Translations}
%%
%% The "author" command and its associated commands are used to define
@@ -210,26 +210,26 @@
%% The abstract is a short summary of the work to be presented in the
%% article.
\begin{abstract}
The increasing disparity between application workloads and the capacity of Translation Lookaside Buffers (TLB)
has prompted researchers to explore innovative solutions to mitigate this gap. One such approach involves
leveraging physically contiguous memory and the use of huge pages to optimize TLB utilization. Huge pages,
which group multiple smaller pages into larger ones, reduce TLB miss rates by decreasing the number of entries
required in the TLB, thus improving overall performance. Concurrently, advancements in hardware-level system
security, exemplified by the Capability Hardware Enhanced RISC Instructions (CHERI) architecture, offer
The increasing disparity between application workloads and the capacity of s (TLB)
has prompted researchers to explore innovative solutions to mitigate this gap. One such approach involves
leveraging physically contiguous memory and the use of huge pages to optimize TLB utilization. Huge pages,
which group multiple smaller pages into larger ones, reduce TLB miss rates by decreasing the number of entries
required in the TLB, thus improving overall performance. Concurrently, advancements in hardware-level system
security, exemplified by the Capability Hardware Enhanced RISC Instructions (CHERI) architecture, offer
additional opportunities for improving memory management and security.
CHERI introduces capability-based addressing, a novel approach that enhances system security by
associating capabilities with memory pointers. These capabilities restrict access to memory regions,
thereby fortifying the system against various security threats. Importantly, the mechanisms implemented in
CHERI for enforcing memory protection can also serve as accelerators for standard user-space memory allocators.
By leveraging capability-based addressing, memory allocators can efficiently manage memory resources, ensure
robust security measures are in place, and potentially enhance performance through the integration of huge pages,
CHERI introduces capability-based addressing, a novel approach that enhances system security by
associating capabilities with memory pointers. These capabilities restrict access to memory regions,
thereby fortifying the system against various security threats. Importantly, the mechanisms implemented in
CHERI for enforcing memory protection can also serve as accelerators for standard user-space memory allocators.
By leveraging capability-based addressing, memory allocators can efficiently manage memory resources, ensure
robust security measures are in place, and potentially enhance performance through the integration of huge pages,
further improving TLB efficiency and memory handling.
Through our evaluation using both micro and macro benchmarks,
we show that our allocator can reduce TLB misses by up to 90\%,
leading to substantial improvements in wall clock runtimes for memory-intensive
applications.
Through our evaluation using both micro and macro benchmarks,
we show that our allocator can reduce TLB misses by up to 90\%,
leading to substantial improvements in wall clock runtimes for memory-intensive
applications.
\end{abstract}
%%
@@ -292,23 +292,23 @@
\maketitle
\section{Introduction}
% In the dynamic landscape of computing, the pursuit of optimal performance is a constant endeavor,
% especially as applications evolve to handle increasingly complex workloads.
% One critical aspect influencing performance is memory management, where efficient
% utilization of resources is paramount. Translation Lookaside Buffers (TLBs) play a
% In the dynamic landscape of computing, the pursuit of optimal performance is a constant endeavor,
% especially as applications evolve to handle increasingly complex workloads.
% One critical aspect influencing performance is memory management, where efficient
% utilization of resources is paramount. s (TLBs) play a
% pivotal role in this regard, expediting memory access by storing recently accessed memory translations.
% However, as applications grow in size and complexity, the capacity of TLBs often struggles to
% keep pace, leading to performance bottlenecks\cite{mittalsurvey2017}. To address this challenge, researchers have
% However, as applications grow in size and complexity, the capacity of TLBs often struggles to
% keep pace, leading to performance bottlenecks~\cite{mittalsurvey2017}. To address this challenge, researchers have
% turned to innovative solutions, one of which involves harnessing the benefits of huge pages.
% Huge pages, also known as large pages, allow for the allocation of memory in significantly
% larger chunks compared to traditional small pages. By reducing the number of TLB entries
% needed to access a given amount of memory, huge pages offer a potential avenue for optimizing
% Huge pages, also known as large pages, allow for the allocation of memory in significantly
% larger chunks compared to traditional small pages. By reducing the number of TLB entries
% needed to access a given amount of memory, huge pages offer a potential avenue for optimizing
% TLB utilization and thereby enhancing overall system performance.
% Simultaneously, advancements in hardware-level security, such as the Capability Hardware
% Enhanced RISC Instructions (CHERI) architecture, present additional opportunities for
% performance enhancement. CHERI's capability-based addressing approach not only strengthens
% system security by tightly controlling memory access but also provides avenues for
% Simultaneously, advancements in hardware-level security, such as the Capability Hardware
% Enhanced RISC Instructions (CHERI) architecture, present additional opportunities for
% performance enhancement. CHERI's capability-based addressing approach not only strengthens
% system security by tightly controlling memory access but also provides avenues for
% accelerating memory management operations.
In computing, achieving high performance is an ongoing challenge, especially as
@@ -319,79 +319,156 @@ memory address translations. A TLB, a specialised cache in the memory management
reduces the time required to convert virtual addresses to physical ones. When a program accesses
data in memory, the MMU first checks the TLB for a matching entry, avoiding the slower process of
consulting page tables. However, as applications grow larger and more complex, the fixed size of
TLBs often cannot keep up, leading to more TLB misses and performance slowdowns\cite{mittal_survey_2017}.
TLBs often cannot keep up, leading to more TLB misses and performance slowdowns~\cite{mittal_survey_2017}.
To tackle this issue, researchers have explored new solutions, including the use of
huge pages\cite{panwar_hawkeye_2019}.
huge pages~\cite{panwar_hawkeye_2019}.
Huge pages, also known as large pages, allow for the allocation of memory in significantly larger chunks
compared to traditional small pages. By reducing the number of TLB entries needed to access a given amount
of memory, Huge pages offer a potential avenue for optimising TLB utilisation by reducing the number
of entries needed to map large memory regions. This not only decreases the frequency of
TLB misses but also lowers the overhead associated with address translation. By minimising
these bottlenecks, huge pages can improve system performance in several ways, such as speeding
these bottlenecks, huge pages can improve system performance in aspects such as speeding
up memory-intensive applications, reducing latency in data access, and enhancing throughput for
workloads that rely heavily on large datasets.
Simultaneously, advancements in hardware-level security, such as the Capability Hardware Enhanced RISC Instructions (CHERI)
\cite{woodruff_cheri_2014} architecture, present additional opportunities for performance enhancement. CHERI's capability-based addressing approach not
~\cite{woodruff_cheri_2014} architecture, present additional opportunities for performance enhancement. CHERI's capability-based addressing approach not
only strengthens system security by tightly controlling memory access but also opens avenues for optimising memory management
operations. By integrating CHERI’s compressed\cite{woodruff_cheri_2019} encoded bounds with the use of huge pages, it becomes possible to track and manage
large, physically contiguous memory blocks more efficiently. This combination reduces TLB pressure by minimising the number of
operations. By integrating CHERI’s compressed~\cite{woodruff_cheri_2019} encoded bounds with the use of huge pages, We have shown it is possible to track and manage
large, physically contiguous memory blocks without requiring numerous TLB entries. This combination reduces TLB pressure by minimising the number of
entries required to map extensive memory regions, thereby decreasing TLB misses and improving address translation performance.
Furthermore, it accelerates memory-intensive tasks by reducing the overhead associated with managing fragmented or non-contiguous
memory allocations. The contributions for the following paper are as follows:
\begin{itemize}
\item \textbf{Fat-pointer Based Range Addresses}: Introduces fat-pointers that include memory bounds, allowing
efficient tracking and management of physically contiguous memory regions.
\item \textbf{Fat pointer Based Range Addresses}: Introduces fat-pointers that include memory bounds, allowing
efficient tracking and management of physically contiguous memory regions (section ~\ref{sec:FatPointerTranslations}).
\item \textbf{Novel Memory Allocation Algorithms}: Provides new algorithms for allocating and freeing
physically contiguous memory, integrating huge pages with CHERI's capability-based bounds for enhanced memory management.
\item \textbf{CHERI’s Capability-based Optimization}: Demonstrates how CHERI's architecture can be
used to optimize memory allocation by encoding memory bounds directly within pointers, reducing TLB reliance.
\end{itemize}
\item \textbf{CHERI’s Capability-based Optimization}: Demonstrates how CHERI's architecture can be
used to optimize memory allocation by encoding memory bounds directly within pointers, reducing TLB reliance
(section ~\ref{sec:128bitCompressedBounds}).
\item \textbf{Memory Allocation Algorithms}: Provides new algorithms for allocating and freeing
physically contiguous memory, integrating huge pages with CHERI's capability-based bounds for enhanced memory management
(section ~\ref{sec:MemoryAllocator}).
\end{itemize}
Through comprehensive evaluation, including micro and macro benchmarks, we demonstrate the allocator’s ability
to reduce TLB misses by up to 90\%, yielding significant improvements in wall clock runtimes for memory-intensive
applications. While its impact on larger, computation-heavy workloads is less pronounced,
the proposed allocator shows strong potential for advancing memory management in scenarios requiring
high memory throughput and low translation overhead.
\newline
\begin{enumerate}
\item How does the utilization of bounds for tracking memory allocations, in addition to security purposes, affect the
run times and Translation Lookaside Buffer (TLB) miss rates in modern computing systems?
\item How does the implementation of bounds for seeking through physically contiguous memory influence the complexity and
efficiency of standard memory allocators, particularly those with advanced features such as transparent
huge pages, and what are the implications for system performance in terms of execution speed, memory access
latency, and resource utilization?
\end{enumerate}
\section{Related work}
\label{sec:org0e192da}
\subsection{Huge Pages}
% A segment~\cite{basu_efficient_nodate} can be viewed as mapping between contiguous virtual
% memory and contiguous physical memory. The property of a
% segment allows it to be larger than a page. Direct Segment allows the user to set a single segment
% for an application. Two registers are added to mark the start
% and end of the segment. Any virtual address within this region
% can be translated by adding the fixed offset between the virtual
% and physical address.
Increasing TLB reach can be achieved by using larger page sizes, such as huge pages~\cite{panwar_hawkeye_2019}, which are common in modern computer systems.
The x86-64 architecture supports huge pages of 2 MB and 1 GB, backed by OS mechanisms like Transparent Huge Pages (THP)~\cite{THP}
and HugeTLBFS in Linux. However, available page sizes in x86-64 are limited, leading to internal fragmentation issues.
% Alternate segment technique
% - JayneelGandhi,ArkapravaBasu,MarkD.Hill,andMichaelM.Swift.2014.Efficientmemoryvirtualization:Reducing
For instance, allocating 1 MB with 4 KB base pages requires 256 PTEs, but using a 2 MB huge page would waste
half of the memory space. Some architectures offer more page size choices, such as Intel Itanium, which
allows different areas of the address space to have their own page sizes. Itanium uses a hash page table to organize huge
pages, but without significant changes to the conventional page table, it only helps reduce page walk overheads.
HP Tunable Base Page Size permits the OS to adjust the base page size, but still faces internal fragmentation problems,
with HP recommending a base page size of no more than 16 KB. Shadow Superpage~\cite{Shadow_superpages} introduces a new translation level
in the memory controller to merge non-contiguous physical pages into a huge page in a shadow memory space, extending
TLB coverage. However, this approach requires all memory traffic to be translated again in the memory controller,
resulting in additional latency for memory accesses.
\subsection{Direct Segment}
Early processors often used segments to manage virtual memory, where a segment~\cite{DirectSegment} essentially mapped contiguous
virtual memory to contiguous physical memory. Unlike pages, which are relatively small, segments can be much
larger, offering the potential for more efficient memory management in certain scenarios.
This concept of segmentation has seen a resurgence in some modern approaches that aim to enhance
translation coverage by designating specific areas in the virtual address space.
This method allows programmers to explicitly define
a single segment for applications requiring significant memory. It introduces two new
registers to the system, which indicate the start and end of this segment.
Virtual addresses within this segment are translated by calculating
the offset from the virtual start address and applying this offset to the
physical start address. This straightforward method simplifies the translation
process for large memory areas but requires significant modifications to the
source code of applications.
\subsection{Range Memory Mapping (RMM)}
Redundant Memory Mappings (RMM)~\cite{karakostas_redundant_2015} enhance memory management by introducing an additional range table
that pre-allocates contiguous physical pages for large memory allocations, creating ranges that
are both virtually and physically contiguous. This approach simplifies address translation
within these ranges by adding an offset, similar to Direct Segment, but RMM supports multiple
ranges and operates transparently to programmers, requiring no source code modifications.
The range table, separate from the conventional page table, holds the mappings for these
large allocations. To determine which range an address belongs to, RMM compares the address
against all range boundaries, a process that is computationally expensive and therefore performed
only after an L1 TLB miss. To optimize this, RMM uses a range TLB (RTLB) to quickly identify
if an address falls within any pre-allocated range, facilitating efficient translation and
reducing overhead. Range mapping works alongside the paging system by generating TLB entries on
TLB misses and still performing TLB lookups for each virtual address translation.
Unlike traditional segmentation mechanisms, range mapping activates a range lookaside
buffer (RTLB) located with the last level TLB upon a miss. The hardware TLB miss
handler then searches the RTLB for the miss address and, if found, generates a new
TLB entry with the physical address derived from the base virtual address and
range offset, along with permission bits. If the RTLB also misses, the system
defaults to a standard page walk while a range table walker simultaneously
loads the range into the RTLB in the background, avoiding delays in memory operations.
The RTLB, functioning as a fully associative search structure, ensures
that most last level TLB misses are handled efficiently by range mapping,
reducing the need for costly page table walks.
\subsection{CHERI}
\label{sec:orgbf2eaac}
CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional processor
Instruction-Set Architectures (ISAs) with architectural capabilities to enable fine-grained
memory protection and highly scalable software compartmentalization. CHERI is a hybrid
capability architecture that can combine capabilities with conventional MMU (Memory Management Unit) based systems.
The contributions of CHERI include:
\begin{itemize}
\item ISA changes to introduce architectural capabilities.
\item New microarchitecture proving that capabilities can be implemented efficiently in hardware, with support for
efficient tagged memory to protect capabilities and compress capabilities to reduce memory overhead.
\item A newly designed software construction model that uses capabilities to provide fine-grained memory protection
and scalable software compartmentalization.
\item Language and compiler extensions for using capabilities with C and C++.
\item OS extensions to support fine-grained memory protection (spatial, referential, and (non-stack) temporal memory safety)
and abstraction extensions for scalable software compartmentalization.
\end{itemize}
\section{Fat-pointer Address Translations}
\section{Fat Address Translations}
\label{sec:FatPointerTranslations}
Fat-pointer Address Translations, combined with the capabilities of the CHERI (Capability Hardware Enhanced RISC Instructions)
architecture, introduce robust memory safety and security features by incorporating additional metadata
with memory pointers. Fat-pointer Address Translations enhanced architecture utilizes concepts such as FlexPointer\cite{chen_flexpointer_2023},
Range Memory Mapping (RMM)\cite{karakostas_redundant_2015} to manage memory effectively.
with memory pointers. Fat-pointer Address Translations enhanced architecture utilizes concepts such as FlexPointer~\cite{chen_flexpointer_2023},
Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to manage memory effectively.
Range addresses play a pivotal role within this implementation, defining memory
Range addresses play a pivotal role within the Fat Address Translations implementation, defining memory
regions bounded by a starting address (Upper) and an ending address (Lower).
These range addresses are encoded within FAT-pointers, allowing for precise
control using CHERI CC\cite{woodruff_cheri_2019} bounds over memory regions to reduce the number of TLB operations needed.
control using CHERI CC~\cite{woodruff_cheri_2019} bounds over memory regions to reduce the number of TLB operations needed.
% The functionality of ranges encompasses several key aspects:
% \begin{itemize}
% \item \textbf{Creation of Physically Contiguous Memory Ranges}:
% By defining memory regions that are physically contiguous, systems can
% By defining memory regions that are physically contiguous, systems can
% achieve optimal memory access patterns, enhancing performance and efficiency.
% \item \textbf{Encoding Ranges as Bounds to the Pointer}:
% Integrating range bounds directly into FAT-pointers enables the architecture
% to enforce memory access restrictions at the pointer level thus allowing
% Integrating range bounds directly into FAT-pointers enables the architecture
% to enforce memory access restrictions at the pointer level thus allowing
% tracking of memory ranges on a pointer level.
% \item \textbf{Instrumenting Block-Based Allocators with Physically Contiguous Memory}:
% The integration of range-based memory concepts into memory allocation systems, such as block-based
% allocators, facilitates the efficient management and utilization of physically contiguous memory blocks,
% The integration of range-based memory concepts into memory allocation systems, such as block-based
% allocators, facilitates the efficient management and utilization of physically contiguous memory blocks,
% mitigating issues related to memory fragmentation.
% \end{itemize}
@@ -403,7 +480,7 @@ control using CHERI CC\cite{woodruff_cheri_2019} bounds over memory regions to r
\end{figure*}
Figure \ref{fig:HighOverviewArchitecture} illustrates
the methodology employed to leverage the CHERI
the methodology employed to use the CHERI
128-bit FAT-pointer scheme for facilitating
block-based memory management on physically
contiguous memory,which is depicted on the
@@ -415,8 +492,6 @@ We explore how using huge pages
with CHERI bounds can reduce the
number of TLB entries required.
The functionality of ranges encompasses several key aspects:
\subsection{Encoding Ranges as Bounds to the Pointer}
\begin{figure}[h]
\includegraphics[width=0.4\textwidth]{diagram/AllocationOverview24.png}
@@ -427,52 +502,54 @@ Integrating range bounds directly into FAT-pointers enables the CHERI architectu
to enforce memory access restrictions at the pointer level thus allowing
tracking of memory ranges on a pointer level. In this implementation, memory ranges are established using
bounds encoded within the FAT-pointer, adhering to the CHERI
128-bit bounds compression scheme\cite{woodruff_cheri_2019}.
128-bit bounds compression scheme~\cite{woodruff_cheri_2019}.
Figure \ref{fig:RangeOfMemory} illustrates a straightforward use-case in which the dark pink line represents a single,
large contiguous memory area, or huge page. Within this huge page, the orange and blue lines indicate
two separate memory allocations equivalent to invoking malloc twice to allocate memory in distinct regions.
This scenario simulates a block-based memory allocator operating within the confines of the huge page.
The allocations leverage the bounds encoded in the FAT-pointer, ensuring tracking of the allocated memory regions. By using the FAT-pointer bounds, this method maintains the
The allocations use the bounds encoded in the FAT-pointer, ensuring tracking of the allocated memory regions.
By using the FAT-pointer bounds, this method maintains the
integrity and contiguity of the allocated blocks within the huge page.
\subsection{128 bit compressed bounds}
\label{sec:128bitCompressedBounds}
% We use CHERI CC (Compressed bounds) to track regions of memory used in physically
% contigous space. CHERI CC consists of bounds which are compressed and represent a
% 128 bit pointer with a 64 bit virtual address system. Our appproach is to use
% a constant single cycle to encode and decode bounds. CHERI CC was originally intended
% for memory protection but can also be repurposed for tracking memory region rather
% than using the standard approach with consists of numerous TLB entries for each allocation.
% contigous space. CHERI CC consists of bounds which are compressed and represent a
% 128 bit pointer with a 64 bit virtual address system. Our appproach is to use
% a constant single cycle to encode and decode bounds. CHERI CC was originally intended
% for memory protection but can also be repurposed for tracking memory region rather
% than using the standard approach with consists of numerous TLB entries for each allocation.
% One of the key analysis highlighted by CHERI CC is that allocators such as Jemalloc always
% allocate objects under 512 bytes. When a bound of an object cannot be represented it is required
% to be padded to memory. It was noted that allocators just as Jemalloc in practice do not require
% more than 6 bits to represent exponents needed within the compressed bounds.
% to be padded to memory. It was noted that allocators just as Jemalloc in practice do not require
% more than 6 bits to represent exponents needed within the compressed bounds.
% This means the default behavoir of most allocators such as Jemalloc would precisely represent bounds
% within the FAT-Pointer which can be repurposed as ranges in memory allocators with custom allocation
% sizes rather than fixed sized TLB entries.
% within the FAT-Pointer which can be repurposed as ranges in memory allocators with custom allocation
% sizes rather than fixed sized TLB entries.
We use CHERI CC\cite{woodruff_cheri_2019} (Compressed Capabilities) to track regions of memory in physically contiguous space.
CHERI CC consists of compressed bounds that represent a 128-bit pointer within a 64-bit virtual address
system. Our approach utilizes a single-cycle encoding and decoding mechanism for efficiency. While CHERI
CC was originally designed for memory protection, it can also be repurposed for tracking memory regions,
We use CHERI CC~\cite{woodruff_cheri_2019} (Compressed Capabilities) to track regions of memory in physically contiguous space.
CHERI CC consists of compressed bounds that represent a 128-bit pointer within a 64-bit virtual address
system. Our approach utilizes a single-cycle encoding and decoding mechanism for efficiency. While CHERI
CC was originally designed for memory protection, it can also be repurposed for tracking memory regions,
eliminating the need for multiple TLB entries for each allocation.
One key analysis of CHERI CC highlights that allocators like Jemalloc typically allocate objects under
512 bytes. When an object’s bounds cannot be precisely represented, padding is required to ensure
memory safety. However, it has been observed that Jemalloc rarely needs more than 6 bits to store the
One key analysis of CHERI CC highlights that allocators like Jemalloc typically allocate objects under
512 bytes. When an object’s bounds cannot be precisely represented, padding is required to ensure
memory safety. However, it has been observed that Jemalloc rarely needs more than 6 bits to store the
exponent values within compressed bounds.
This means that the default behavior of most allocators, such as Jemalloc, would allow precise
representation of bounds within a FAT-pointer. These pointers can then be repurposed as memory ranges
This means that the default behavior of most allocators, such as Jemalloc, would allow precise
representation of bounds within a FAT-pointer. These pointers can then be repurposed as memory ranges
in custom memory allocators, offering a more flexible alternative to fixed-size TLB entries.
% \subsection{Creation of Physically Contiguous Memory Ranges}
% \smallskip\noindent
% The memory chunk defined by the upper and lower bounds is always physically contiguous.
% By defining memory regions that are physically contiguous, systems can
% By defining memory regions that are physically contiguous, systems can
% achieve optimal memory access patterns, enhancing performance and efficiency.
\subsection{Instrumenting Block-Based Allocators with Physically Contiguous Memory}
@@ -486,7 +563,7 @@ structures to map virtual addresses to physical addresses.
This often requires multiple entries to handle different
memory segments, which increases overhead and adds complexity
to the translation process. In contrast, Our approach
simplifies this by using a single TLB
simplifies this by using a single TLB
entry to translate multiple addresses within a contiguous memory
range. This reduces the number of TLB entries needed, making the
translation process more efficient and less complex.
@@ -507,7 +584,8 @@ bounds for that particular pointer access. Using bounds
stored on the pointer a block based pattern can be reprecated
on physically contigous memory.
\subsection{Sample memory allocator design:}
\section{Memory allocator design}
\label{sec:MemoryAllocator}
This section presents a straightforward memory allocator designed and implemented based on the
principles outlined in our approach. The allocator consists of three core functions: InitAlloc,
malloc, and free. The InitAlloc function initializes the memory pool, setting up the necessary
@@ -523,7 +601,7 @@ such as Jemalloc, enabling them to operate with significantly lesser L1 TLB miss
contiguity is essential.
\begin{algorithm}
\caption{Sample malloc implementation}
\caption{Malloc implementation}
\label{alg:malloc}
\begin{algorithmic}[1]
\Function{malloc}{sz}
@@ -536,21 +614,21 @@ contiguity is essential.
\end{algorithmic}
\end{algorithm}
When the malloc function (Algorithm \ref{alg:malloc}) is invoked, the algorithm employs an eager allocation strategy for physical memory.
When the malloc function (Algorithm \ref{alg:malloc}) is invoked, the algorithm employs an eager allocation strategy for physical memory.
This is achieved through the use of the SetBounds mechanism, which constructs a FAT-pointer specialized
pointer that encodes both the start and end addresses of the allocated memory region within the pointer
itself. The start and end addresses correspond to the size of the memory block requested by malloc. This
approach introduces a method of memory tracking, where the bounds of the allocated region are
explicitly encoded in the address, enabling efficient monitoring and management of memory usage.
Furthermore, this design leverages shared huge page TLB (Translation Lookaside Buffer) entries to map
Furthermore, this design uses shared huge page TLB entries to map
and track memory addresses. By encoding bounds directly into the address, the algorithm ensures that memory
accesses remain within the allocated region, thereby enhancing safety and reducing the risk of out-of-bounds
errors. This use of FAT-pointers and shared TLB entries not only aligns with the principles of
efficient memory management but also demonstrates a practical usecase of huge pages in CHERI.
\begin{algorithm}
\caption{Sample free implementation}
\caption{Free implementation}
\label{alg:free}
\begin{algorithmic}[1]
\Function{free}{ptr}
@@ -564,9 +642,9 @@ efficient memory management but also demonstrates a practical usecase of huge pa
introduced in the malloc algorithm. When the free function is invoked, it utilizes the metadata
embedded within the FAT-pointer to determine the range and size of the allocated memory region.
Specifically, the start and end addresses encoded in the FAT-pointer provide the necessary information
to identify the exact memory block to be deallocated. This allows the allocator to precisely unmapped
to identify the exact memory block to be deallocated. This allows the allocator to precisely unmap
the corresponding memory region from the address space, ensuring efficient and accurate memory management.
By extracting the bounds and size directly from the FAT-pointer, the free function eliminates the need
for additional metadata lookups or complex data structures, streamlining the deallocation process.
This approach not only enhances performance but also reduces the risk of memory leaks or fragmentation.
@@ -574,7 +652,7 @@ efficient memory management but also demonstrates a practical usecase of huge pa
\begin{algorithm}
\caption{Sample init alloc function to create a initial 1 GB huge page}
\caption{Init alloc function to create a initial 1 GB huge page}
\label{alg:initAlloc}
\begin{algorithmic}[1]
\Function{Init\_alloc}{}
@@ -595,11 +673,10 @@ with page table management and enhances memory access efficiency, which is criti
applications and kernel-level operations.
\section{Evaluation}
We conducted tests of the FAT Pointer-based range addresses against Jemalloc\cite{jemalloc},
the default memory allocator for CHERIBSD\cite{cheribsd}, to assess the performance improvements
We conducted tests of the FAT Pointer-based range addresses against Jemalloc~\cite{jemalloc},
the default memory allocator for CHERIBSD~\cite{cheribsd}, to assess the performance improvements
enabled by a CHERI-based huge page-aware allocator. Specifically, we evaluated
the reduction in TLB misses and its impact on overall
performance metrics, such as wall clock runtime.
the reduction in TLB walks and misses and its impact on wall clock runtime.
To comprehensively analyze the proposed allocator, we categorized benchmarks into
two classes which are micro and macro benchmarks. Micro benchmarks comprise smaller
@@ -633,8 +710,8 @@ However, limitations were also identified, such as scenarios where the allocator
gains were marginal or where it introduced additional complexity in memory management. These
limitations provide a roadmap for future optimizations and refinements of the allocator design.
\subsection{Expirement setup}
The CHERI Morello\cite{Morello} board was used to evaluate the proposed memory allocator.
\subsection{Experiment setup}
The CHERI Morello~\cite{Morello} board was used to evaluate the proposed memory allocator.
Morello implements the ARM A76 with enhanced server-class memory, featuring a
quad-core ARM CPU with capability extensions. The L1 and L2 caches were modified
to proliferate the capability bit, ensuring compatibility with CHERI's capability-based
@@ -642,7 +719,7 @@ memory model. When compiling the C programs for benchmarking, the Benchmark ABI
used as recommended by the CHERI community. This compilation mode was enabled using
the Clang compiler.
The Benchmark ABI\cite{BenchmarkABI} was specifically designed because the Morello branch predictor
The Benchmark ABI~\cite{BenchmarkABI} was specifically designed because the Morello branch predictor
was not expanded to predict bounds. Consequently, a capability-based jump introduces
stalls in later PCC-dependent instructions until bounds are established. This issue
is particularly significant during dynamically linked calls and returns between
@@ -657,7 +734,7 @@ failing to overwrite the C program at runtime with the intended malloc functions
The second allocator was the standard OS memory allocator, which, in the case of
CHERIBSD, is Jemalloc.
Performance measurements were carried out using ARM performance counters\cite{PerformanceCounter} to
Performance measurements were carried out using ARM performance counters~\cite{PerformanceCounter} to
ensure accurate evaluation. These counters provided detailed metrics, allowing
us to compare the performance of the two allocators and assess the impact of
the proposed changes.
@@ -705,12 +782,9 @@ the proposed changes.
\end{table*}
\subsection{Benchmarks}
The benchmarks\cite{Benchmark} are classified into 2 classes:
The benchmarks~\cite{Benchmark} are classified into 2 classes:
\subsubsection{Micro benchmark}
\begin{enumerate}
\item Micro benchmark
\label{sec:org41c278c}
\begin{itemize}
\item GLIBC: The Glibc benchmark evaluates the performance of
@@ -727,7 +801,7 @@ The benchmarks\cite{Benchmark} are classified into 2 classes:
doubles the working set size to analyze memory hierarchy behavior.
\end{itemize}
\item Macro runs
\subsubsection{Macro benchmark}
\label{sec:org89020f2}
\begin{itemize}
\item Kmeans: Kmeans implements a parallelized K-means clustering algorithm that
@@ -744,7 +818,6 @@ task execution based on state and priority, tracking processed packets
and held tasks for performance evaluation. Configurable iterations and
timing help measure system performance and ensure correctness.
\end{itemize}
\end{enumerate}
\subsection{Results}
@@ -753,7 +826,7 @@ timing help measure system performance and ensure correctness.
\caption{\label{fig:bargraph}Percentage difference between the modified memory allocator against the default system memory allocator}
\end{figure*}
The graph (Diagram \ref{fig:bargraph}) highlights the performance comparison between the modified memory allocator and
The graph (Figure \ref{fig:bargraph}) highlights the performance comparison between the modified memory allocator and
Jemalloc, the default memory allocator. The FAT pointer memory allocator, specifically optimized
for use with huge pages, demonstrates a clear advantage in scenarios where memory allocation
patterns benefit from its design. The results align with expectations, showcasing the impact
@@ -788,7 +861,7 @@ bottlenecked by factors such as computation or I/O rather than memory translatio
The K-means algorithm was executed with varying cluster sizes to evaluate the performance difference
between the FAT pointer allocator and the baseline allocator as the workload scales. This analysis
aimed to understand how the allocator's optimizations, particularly its ability to manage memory
aims to understand how the allocator's optimizations, particularly its ability to manage memory
more efficiently with huge pages, impact performance under different workload conditions.
For most cluster sizes tested, the percentage difference in performance remained relatively
@@ -799,8 +872,7 @@ and efficiently manage memory allocations for the centroid and data point struct
the K-means algorithm.
However, an anomaly was observed at a cluster size of 2000, where the percentage difference
deviated significantly from the trend. This irregularity could be attributed to several factors.
At this cluster size, the memory access patterns and allocation behavior may align in a way that
deviated significantly from the trend. At this cluster size, the memory access patterns and allocation behavior may align in a way that
temporarily offsets the advantages of the FAT pointer allocator. For example, the memory layout
might interact with system-level caching mechanisms or TLB behavior differently, leading to an
unexpected change in performance. Additionally, the increased complexity of managing a higher
@@ -833,96 +905,11 @@ macro benchmarks is less pronounced. This suggests that its benefits are most re
applications with frequent and intensive memory operations rather than those constrained by
computation or I/O bottlenecks.
\section{Related work}
\label{sec:org0e192da}
\subsection{Huge Pages}
% A segment\cite{basu_efficient_nodate} can be viewed as mapping between contiguous virtual
% memory and contiguous physical memory. The property of a
% segment allows it to be larger than a page. Direct Segment allows the user to set a single segment
% for an application. Two registers are added to mark the start
% and end of the segment. Any virtual address within this region
% can be translated by adding the fixed offset between the virtual
% and physical address.
Increasing TLB reach can be achieved by using larger page sizes, such as huge pages\cite{panwar_hawkeye_2019}, which are common in modern computer systems.
The x86-64 architecture supports huge pages of 2 MB and 1 GB, backed by OS mechanisms like Transparent Huge Pages (THP)\cite{THP}
and HugeTLBFS in Linux. However, available page sizes in x86-64 are limited, leading to internal fragmentation issues.
% Alternate segment technique
% - JayneelGandhi,ArkapravaBasu,MarkD.Hill,andMichaelM.Swift.2014.Efficientmemoryvirtualization:Reducing
For instance, allocating 1 MB with 4 KB base pages requires 256 PTEs, but using a 2 MB huge page would waste
half of the memory space. Some architectures offer more page size choices, such as Intel Itanium, which
allows different areas of the address space to have their own page sizes. Itanium uses a hash page table to organize huge
pages, but without significant changes to the conventional page table, it only helps reduce page walk overheads.
HP Tunable Base Page Size permits the OS to adjust the base page size, but still faces internal fragmentation problems,
with HP recommending a base page size of no more than 16 KB. Shadow Superpage\cite{Shadow_superpages} introduces a new translation level
in the memory controller to merge non-contiguous physical pages into a huge page in a shadow memory space, extending
TLB coverage. However, this approach requires all memory traffic to be translated again in the memory controller,
resulting in additional latency for memory accesses.
\subsection{Direct Segment}
Early processors often used segments to manage virtual memory, where a segment\cite{DirectSegment} essentially mapped contiguous
virtual memory to contiguous physical memory. Unlike pages, which are relatively small, segments can be much
larger, offering the potential for more efficient memory management in certain scenarios.
This concept of segmentation has seen a resurgence in some modern approaches that aim to enhance
translation coverage by designating specific areas in the virtual address space.
This method allows programmers to explicitly define
a single segment for applications requiring significant memory. It introduces two new
registers to the system, which indicate the start and end of this segment.
Virtual addresses within this segment are translated by calculating
the offset from the virtual start address and applying this offset to the
physical start address. This straightforward method simplifies the translation
process for large memory areas but requires significant modifications to the
source code of applications.
\subsection{Range Memory Mapping (RMM)}
Redundant Memory Mappings (RMM)\cite{karakostas_redundant_2015} enhance memory management by introducing an additional range table
that pre-allocates contiguous physical pages for large memory allocations, creating ranges that
are both virtually and physically contiguous. This approach simplifies address translation
within these ranges by adding an offset, similar to Direct Segment, but RMM supports multiple
ranges and operates transparently to programmers, requiring no source code modifications.
The range table, separate from the conventional page table, holds the mappings for these
large allocations. To determine which range an address belongs to, RMM compares the address
against all range boundaries, a process that is computationally expensive and therefore performed
only after an L1 TLB miss. To optimize this, RMM uses a range TLB (RTLB) to quickly identify
if an address falls within any pre-allocated range, facilitating efficient translation and
reducing overhead. Range mapping works alongside the paging system by generating TLB entries on
TLB misses and still performing TLB lookups for each virtual address translation.
Unlike traditional segmentation mechanisms, range mapping activates a range lookaside
buffer (RTLB) located with the last level TLB upon a miss. The hardware TLB miss
handler then searches the RTLB for the miss address and, if found, generates a new
TLB entry with the physical address derived from the base virtual address and
range offset, along with permission bits. If the RTLB also misses, the system
defaults to a standard page walk while a range table walker simultaneously
loads the range into the RTLB in the background, avoiding delays in memory operations.
The RTLB, functioning as a fully associative search structure, ensures
that most last level TLB misses are handled efficiently by range mapping,
reducing the need for costly page table walks.
\subsection{CHERI}
\label{sec:orgbf2eaac}
CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional processor
Instruction-Set Architectures (ISAs) with architectural capabilities to enable fine-grained
memory protection and highly scalable software compartmentalization. CHERI is a hybrid
capability architecture that can combine capabilities with conventional MMU (Memory Management Unit) based systems.
The contributions of CHERI include:
\begin{itemize}
\item ISA changes to introduce architectural capabilities.
\item New microarchitecture proving that capabilities can be implemented efficiently in hardware, with support for
efficient tagged memory to protect capabilities and compress capabilities to reduce memory overhead.
\item A newly designed software construction model that uses capabilities to provide fine-grained memory protection
and scalable software compartmentalization.
\item Language and compiler extensions for using capabilities with C and C++.
\item OS extensions to support fine-grained memory protection (spatial, referential, and (non-stack) temporal memory safety)
and abstraction extensions for scalable software compartmentalization.
\end{itemize}
\section{Future work}
The current experimental setup on the ARM Morello board is constrained by the requirement that all memory reads must
pass through the Translation Lookaside Buffer (TLB) for address translation. This necessitates frequent TLB lookups, potentially
leading to performance bottlenecks. The planned future work aims to address this by leveraging CHERI
(Capability Hardware Enhanced RISC Instructions) extensions on the RISC-V architecture, specifically using the
The current experimental setup on the ARM Morello board is constrained by the requirement that all memory reads must
pass through the (TLB) for address translation. This necessitates frequent TLB lookups, potentially
leading to performance bottlenecks. The planned future work aims to address this by leveraging CHERI
(Capability Hardware Enhanced RISC Instructions) extensions on the RISC-V architecture, specifically using the
Tooba implementation.
\subsection{Storing Offsets Directly on Pointers}
@@ -939,17 +926,17 @@ The Bluespec design of the RISC-V processor will be modified to allow certain me
This modification reduces the dependency on the TLB, decreasing latency and improving performance, especially for frequent memory operations.
\section{Conclusion} %Title of the Conclusion
This paper addresses the growing disparity between application workloads and the capacity of Translation Lookaside Buffers (TLBs).
To mitigate this gap, it proposes leveraging physically contiguous memory to reduce TLB walks. Additionally,
the report explores advancements in system security, particularly through the Capability Hardware Enhanced RISC Instructions (CHERI)
architecture. CHERI's capability-based addressing enhances system security by associating capabilities with memory pointers,
restricting access to memory regions, and thus protecting against various security threats. Importantly, these mechanisms
This paper addresses the growing disparity between application workloads and the capacity of s (TLBs).
To mitigate this gap, it proposes leveraging physically contiguous memory to reduce TLB walks. Additionally,
the report explores advancements in system security, particularly through the Capability Hardware Enhanced RISC Instructions (CHERI)
architecture. CHERI's capability-based addressing enhances system security by associating capabilities with memory pointers,
restricting access to memory regions, and thus protecting against various security threats. Importantly, these mechanisms
can also improve the reduction of TLB walks to memory allocators by using CHERI bounds while maintaining CHERI's security guarantees.
\newline
Comprehensive benchmarking demonstrates that the allocator reduces TLB misses by up to 90\%,
Comprehensive benchmarking demonstrates that the allocator reduces TLB misses by up to 90\%,
leading to substantial performance gains in memory-intensive workloads, though the improvements are less pronounced
for larger, computation-heavy applications. These results highlight the allocator's potential to advance memory management
for larger, computation-heavy applications. These results highlight the allocator's potential to advance memory management
by combining enhanced security and performance through CHERI's capability-based model with the use of huge pages.
@@ -1225,7 +1212,7 @@ by combining enhanced security and performance through CHERI's capability-based
% \texttt{{\char'134}begin\,\ldots{\char'134}end} construction or with
% the short form \texttt{\$\,\ldots\$}. You can use any of the symbols
% and structures, from $\alpha$ to $\omega$, available in
% \LaTeX~\cite{Lamport:LaTeX}; this section will simply show a few
% \LaTeX~~\cite{Lamport:LaTeX}; this section will simply show a few
% examples of in-text equations in context. Notice how this equation:
% \begin{math}
% \lim_{n\rightarrow \infty}x=0
@@ -1336,40 +1323,40 @@ by combining enhanced security and performance through CHERI's capability-based
% command in the {\bfseries preamble} (before the command
% ``\verb|\begin{document}|'') of your \LaTeX\ source:
% \begin{verbatim}
% \citestyle{acmauthoryear}
% ~\citestyle{acmauthoryear}
% \end{verbatim}
% Some examples. A paginated journal article \cite{Abril07}, an
% enumerated journal article \cite{Cohen07}, a reference to an entire
% issue \cite{JCohen96}, a monograph (whole book) \cite{Kosiur01}, a
% Some examples. A paginated journal article ~\cite{Abril07}, an
% enumerated journal article ~\cite{Cohen07}, a reference to an entire
% issue ~\cite{JCohen96}, a monograph (whole book) ~\cite{Kosiur01}, a
% monograph/whole book in a series (see 2a in spec. document)
% \cite{Harel79}, a divisible-book such as an anthology or compilation
% \cite{Editor00} followed by the same example, however we only output
% the series if the volume number is given \cite{Editor00a} (so
% ~\cite{Harel79}, a divisible-book such as an anthology or compilation
% ~\cite{Editor00} followed by the same example, however we only output
% the series if the volume number is given ~\cite{Editor00a} (so
% Editor00a's series should NOT be present since it has no vol. no.),
% a chapter in a divisible book \cite{Spector90}, a chapter in a
% divisible book in a series \cite{Douglass98}, a multi-volume work as
% book \cite{Knuth97}, a couple of articles in a proceedings (of a
% a chapter in a divisible book ~\cite{Spector90}, a chapter in a
% divisible book in a series ~\cite{Douglass98}, a multi-volume work as
% book ~\cite{Knuth97}, a couple of articles in a proceedings (of a
% conference, symposium, workshop for example) (paginated proceedings
% article) \cite{Andler79, Hagerup1993}, a proceedings article with
% all possible elements \cite{Smith10}, an example of an enumerated
% proceedings article \cite{VanGundy07}, an informally published work
% \cite{Harel78}, a couple of preprints \cite{Bornmann2019,
% AnzarootPBM14}, a doctoral dissertation \cite{Clarkson85}, a
% master's thesis: \cite{anisi03}, an online document / world wide web
% resource \cite{Thornburg01, Ablamowicz07, Poker06}, a video game
% (Case 1) \cite{Obama08} and (Case 2) \cite{Novak03} and \cite{Lee05}
% and (Case 3) a patent \cite{JoeScientist001}, work accepted for
% publication \cite{rous08}, 'YYYYb'-test for prolific author
% \cite{SaeediMEJ10} and \cite{SaeediJETC10}. Other cites might
% article) ~\cite{Andler79, Hagerup1993}, a proceedings article with
% all possible elements ~\cite{Smith10}, an example of an enumerated
% proceedings article ~\cite{VanGundy07}, an informally published work
% ~\cite{Harel78}, a couple of preprints ~\cite{Bornmann2019,
% AnzarootPBM14}, a doctoral dissertation ~\cite{Clarkson85}, a
% master's thesis: ~\cite{anisi03}, an online document / world wide web
% resource ~\cite{Thornburg01, Ablamowicz07, Poker06}, a video game
% (Case 1) ~\cite{Obama08} and (Case 2) ~\cite{Novak03} and ~\cite{Lee05}
% and (Case 3) a patent ~\cite{JoeScientist001}, work accepted for
% publication ~\cite{rous08}, 'YYYYb'-test for prolific author
% ~\cite{SaeediMEJ10} and ~\cite{SaeediJETC10}. Other cites might
% contain 'duplicate' DOI and URLs (some SIAM articles)
% \cite{Kirschmer:2010:AEI:1958016.1958018}. Boris / Barbara Beeton:
% multi-volume works as books \cite{MR781536} and \cite{MR781537}. A
% ~\cite{Kirschmer:2010:AEI:1958016.1958018}. Boris / Barbara Beeton:
% multi-volume works as books ~\cite{MR781536} and ~\cite{MR781537}. A
% couple of citations with DOIs:
% \cite{2004:ITE:1009386.1010128,Kirschmer:2010:AEI:1958016.1958018}. Online
% citations: \cite{TUGInstmem, Thornburg01, CTANacmart}.
% Artifacts: \cite{R} and \cite{UMassCitations}.
% ~\cite{2004:ITE:1009386.1010128,Kirschmer:2010:AEI:1958016.1958018}. Online
% citations: ~\cite{TUGInstmem, Thornburg01, CTANacmart}.
% Artifacts: ~\cite{R} and ~\cite{UMassCitations}.
% \section{Acknowledgments}

70
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@@ -0,0 +1,70 @@
### General
- [ ] Change name (Thinking of using (Fat Address Translation) -> similar to GNU))
- [ ] Avoid words which create options
- [x] Use citation with ```~/cite{foo}```
- [ ] Clear distinction on Literature review and contribution done
- [x] Generalise capitalisation
- [ ] Avoid several use ex: There are 3 way...
- [x] Instead of "Leverage" -> "use"
- [ ] Remove whitespace from figures to be compressed
- [ ] Uniform font sizes in figures
- [ ] Symmetrical lines on the figure
- [ ] TLB with acronym only once for the first instance in the paper
### Abstract
- [ ] Reduce Abstract to a single paragraph'
- [ ] "Mitigate gap, capacity" -> Expand on for instance on how is it measured.
- [ ] Huge pages moved to the introduction.
- [ ] Robs proposed structure (This paper presents <NAME> user-space memory allocator. It uses capability-based addressing to <list properties>.
### Introduction
- [ ] "It becomes possible" expand more with baseline compressed bounds.
- [ ] "This paper makes the following contribution" -. bullet points with marked sections.
- [ ] Research questions removed.
- [ ] "This implementation" Specify implementation
- [ ] Robs recommended Introduction structure (Expansion of the abstract, Name of the existing system, clearly describe limitation, Introduce memory allocator).
### 2.1 Encoding ranges as bounds
- [x] Repetition "Tracking of memory ranges using information in pointers" -> remove this
- [ ] Paraphrase last sentence
### 2.2 128 bit compressed bounds
- [x] Cites Jemalloc paragraph.
- [ ] Last sentence needs rewriting.
### 2.3 Instrumenting block based allocator
- [ ] Needs citation "Which increases overhead and adds complexity"
- [ ] Elaborate on "this method"
- [ ] "precise" memory management (Elaborate on this and prove which aspects of the other allocator are not precise).
### Memory allocator design
- [x] Remove from heading "sample" and ":"
- [ ] Remove future work paragraph
- [x] "unmapped" -> unmap
- [ ] "Risks of memory leaks with metadata lookups or complex data structures" -> Elaborate on this
### Evaluation
- [x] Name of the project keeps the sentence shorter.
- [x] "Such as" -> Definitive and exhaustive.
- [ ] TLB misses and walk contextualised better.
- [ ] Section reference on evaluation expanded.
- [ ] Remove "Providing a solid foundation for meaningful comparisons"
- [ ] Decide to use Macro or instead "real world C programs"
- [x] 1st section Evaluation remove "We observed...."
- [x] Experiment section typo heading
- [x] Fix Latex benchmarks structure
- [x] Change from "Diagram" to "Figure"
- [ ] Result para 2 -> too wordy
- [x] "aimed" first use of past tense (Recommendation: avoid)
- [x] Last paragraph (More substance)
- [x] Experiment results systematically explained based on benchmarks as bullet points.
- [ ] Rewrite usability
### Related work
- [ ] Related work lifted up after introduction based on the reflection of the feedback.
### Conclusion
- [ ] Rewrite