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@article{rugg_2022, title={Efficient spatial and temporal safety for microcontrollers and application-class processors}, url={https://www.repository.cam.ac.uk/handle/1810/353468}, DOI={10.17863/CAM.99588}, school={Apollo - University of Cambridge Repository}, author={Rugg, Peter}, year={2022}, keywords={CHERI, Hardware design, Memory safety, RISC-V} }
@article{bluespec,
author = {Nikhil, Rishiyur S. and Arvind},
title = {What is Bluespec?},
year = {2008},
issue_date = {December 2008},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {38},
number = {23},
issn = {0163-5743},
url = {https://doi.org/10.1145/1862867.1862868},
doi = {10.1145/1862867.1862868},
abstract = {Bluespec refers to a language and associated tools which are being used for all aspects of hardware system design . specification, synthesis, modeling, and verification. The language, BSV (Bluespec SystemVerilog), is based on a new model of computation for hardware, where all behavior is described as a set of rewrite rules, or Guarded Atomic Actions. Unlike the process/thread model of Verilog, VHDL and SystemC, or the sequential model of C/C++, all behavior of a BSV program can be understood in terms of atomic rule firings. This computational model has a long pedigree in formal specification and verification systems (e.g., Dijkstra's Guarded Commands, UNITY, TLA+, and EventB), and BSV makes it available for hardware design.},
journal = {SIGDA Newsl.},
month = dec,
pages = {1},
numpages = {1}
}
@incollection{bsv,
address = {Cham},
title = {Bluespec {SystemVerilog}},
isbn = {978-3-319-26408-0},
url = {https://doi.org/10.1007/978-3-319-26408-0_9},
abstract = {Bluespec SystemVerilog (BSV) is a rule-based language, where hardware is described as object-oriented modules. Other high-level synthesis approaches try to hide the complexity of hardware (clock cycles, data movement, concurrency, etc.) under the appearance of a sequential and centralized execution. Instead, BSV exposes it to the user as an intuitive high-level metaphor. This language is a good candidate for expert hardware designers with a background on Register-Transfer Level (RTL) languages, such as Verilog or VHDL, for designers that have to develop critical hardware components, or for keeping a very tight control over the performance and the resources used. This chapter introduces the basic concepts of Bluespec SystemVerilog.},
booktitle = {{FPGAs} for {Software} {Programmers}},
publisher = {Springer International Publishing},
author = {Arcas-Abella, Oriol and Sonmez, Nehir},
editor = {Koch, Dirk and Hannig, Frank and Ziener, Daniel},
year = {2016},
doi = {10.1007/978-3-319-26408-0_9},
pages = {165--172},
}
@article{FlexPointer,
author = {Chen, Dongwei and Tong, Dong and Yang, Chun and Yi, Jiangfang and Cheng, Xu},
title = {FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers},
year = {2023},
issue_date = {June 2023},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {20},
number = {2},
issn = {1544-3566},
url = {https://doi.org/10.1145/3579854},
doi = {10.1145/3579854},
abstract = {Page-based virtual memory relies on TLBs to accelerate the address translation. Nowadays, the gap between application workloads and the capacity of TLB continues to grow, bringing many costly TLB misses and making the TLB a performance bottleneck. Previous studies seek to narrow the gap by exploiting the contiguity of physical pages. One promising solution is to group pages that are both virtually and physically contiguous into a memory range. Recording range translations can greatly increase the TLB reach, but ranges are also hard to index because they have arbitrary bounds. The processor has to compare against all the boundaries to determine which range an address falls in, which restricts the usage of memory ranges. In this article, we propose a tagged-pointer-based scheme, FlexPointer, to solve the range indexing problem. The core insight of FlexPointer is that large memory objects are rare, so we can create memory ranges based on such objects and assign each of them a unique ID. With the range ID integrated into pointers, we can index the range TLB with IDs and greatly simplify its structure. Moreover, because the ID is stored in the unused bits of a pointer and is not manipulated by the address generation, we can shift the range lookup to an earlier stage, working in parallel with the address generation. According to our trace-based simulation results, FlexPointer can reduce nearly all the L1 TLB misses, and page walks for a variety of memory-intensive workloads. Compared with a 4K-page baseline system, FlexPointer shows a 14\% performance improvement on average and up to 2.8x speedup in the best case. For other workloads, FlexPointer shows no performance degradation.},
journal = {ACM Trans. Archit. Code Optim.},
month = mar,
articleno = {30},
numpages = {24},
keywords = {address translation, TLB reach, Tagged pointer}
}
@article{10.1145/2872887.2749471,
author = {Karakostas, Vasileios and Gandhi, Jayneel and Ayar, Furkan and Cristal, Adri\'{a}n and Hill, Mark D. and McKinley, Kathryn S. and Nemirovsky, Mario and Swift, Michael M. and \"{U}nsal, Osman},
title = {Redundant memory mappings for fast access to large memories},
year = {2015},
issue_date = {June 2015},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {43},
number = {3S},
issn = {0163-5964},
url = {https://doi.org/10.1145/2872887.2749471},
doi = {10.1145/2872887.2749471},
abstract = {Page-based virtual memory improves programmer productivity, security, and memory utilization, but incurs performance overheads due to costly page table walks after TLB misses. This overhead can reach 50\% for modern workloads that access increasingly vast memory with stagnating TLB sizes.To reduce the overhead of virtual memory, this paper proposes Redundant Memory Mappings (RMM), which leverage ranges of pages and provides an efficient, alternative representation of many virtual-to-physical mappings. We define a range be a subset of process's pages that are virtually and physically contiguous. RMM translates each range with a single range table entry, enabling a modest number of entries to translate most of the process's address space. RMM operates in parallel with standard paging and uses a software range table and hardware range TLB with arbitrarily large reach. We modify the operating system to automatically detect ranges and to increase their likelihood with eager page allocation. RMM is thus transparent to applications.We prototype RMM software in Linux and emulate the hardware. RMM performs substantially better than paging alone and huge pages, and improves a wider variety of workloads than direct segments (one range per program), reducing the overhead of virtual memory to less than 1\% on average.},
journal = {SIGARCH Comput. Archit. News},
month = jun,
pages = {66–78},
numpages = {13}
}
@inproceedings{rmm,
author = {Karakostas, Vasileios and Gandhi, Jayneel and Ayar, Furkan and Cristal, Adri\'{a}n and Hill, Mark D. and McKinley, Kathryn S. and Nemirovsky, Mario and Swift, Michael M. and \"{U}nsal, Osman},
title = {Redundant memory mappings for fast access to large memories},
year = {2015},
isbn = {9781450334020},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/2749469.2749471},
doi = {10.1145/2749469.2749471},
abstract = {Page-based virtual memory improves programmer productivity, security, and memory utilization, but incurs performance overheads due to costly page table walks after TLB misses. This overhead can reach 50\% for modern workloads that access increasingly vast memory with stagnating TLB sizes.To reduce the overhead of virtual memory, this paper proposes Redundant Memory Mappings (RMM), which leverage ranges of pages and provides an efficient, alternative representation of many virtual-to-physical mappings. We define a range be a subset of process's pages that are virtually and physically contiguous. RMM translates each range with a single range table entry, enabling a modest number of entries to translate most of the process's address space. RMM operates in parallel with standard paging and uses a software range table and hardware range TLB with arbitrarily large reach. We modify the operating system to automatically detect ranges and to increase their likelihood with eager page allocation. RMM is thus transparent to applications.We prototype RMM software in Linux and emulate the hardware. RMM performs substantially better than paging alone and huge pages, and improves a wider variety of workloads than direct segments (one range per program), reducing the overhead of virtual memory to less than 1\% on average.},
booktitle = {Proceedings of the 42nd Annual International Symposium on Computer Architecture},
pages = {66–78},
numpages = {13},
location = {Portland, Oregon},
series = {ISCA '15}
}

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P.~Rugg, ``Efficient spatial and temporal safety for microcontrollers and
application-class processors,'' 2022. [Online]. Available:
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translation based on range tlb and tagged pointers,'' \emph{ACM Trans.
Archit. Code Optim.}, vol.~20, no.~2, Mar. 2023. [Online]. Available:
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* FAT Allocator without the TLB
** Abstract
This document explores an extension of the FAT allocator approach to memory management in RISC-V Toooba.
This document explores an extension of the FAT allocator approach to memory management in RISC-V Toooba\cite{rugg_2022}.
CHERI introduces a fine-grained memory protection mechanism by embedding bounds and permissions directly
within pointers. Leveraging this model, we propose a system in which offsets are stored within the pointer itself, enabling
direct memory access without reliance on traditional address translation mechanisms such as the TLB. This method
@@ -10,7 +10,7 @@ are the technique expected to be used and the evaluation criteria for the follow
** Research questions
1. How can embedding offsets within a FAT pointer (i.e CHERI pointer) improve memory accesses for a block-based allocator for the RISC-V CHERI modified Toooba architecture ?
2. To what extent does eliminating TLB impact the reduction in CPU clock cycles and memory access latency in a physically contiguous memory ?
2. To what extent does eliminating TLB impact the reduction in CPU clock cycles and memory access latency ?
** Proposed approach
#+attr_latex: :width 300px
@@ -20,7 +20,7 @@ are the technique expected to be used and the evaluation criteria for the follow
FAT-Pointers based range addresses, combined with the capabilities of the CHERI architecture, introduce
bypassing the TLB hierarchy by incorporating additional metadata with memory pointers.
This enhanced architecture utilises concepts such as FlexPointer, Range Memory Mapping (RMM) to manage memory as customised sizes rather than groups
This enhanced architecture utilises concepts such as FlexPointer\cite{FlexPointer}, Range Memory Mapping (RMM)\cite{rmm} to manage memory as customised sizes rather than groups
of fixed page sizes. Range addresses play a pivotal role within this framework, defining memory regions bounded by a starting address
(Upper) and an ending address (Lower). These range addresses are encoded within FAT-pointers, allowing for precise control
over memory regions. The functionality of ranges encompasses several key aspects:
@@ -29,10 +29,9 @@ over memory regions. The functionality of ranges encompasses several key aspects
- Encoding Ranges as Bounds to the Pointer.
- Instrumenting Block-Based Allocators with the FAT Pointer.
In figure 2.1, the green-highlighted section marks the unused space between the 48th and 64th bits
In figure [[fig:RFPBRA]], the green-highlighted section marks the unused space between the 48th and 64th bits
within the FAT-pointer. This area of unused bits presents an opportunity to store additional metadata,
potentially enhancing the capabilities of the memory management system. Here we explore how this additional
metadata storage could be used to further optimise memory allocation.
potentially enhancing the capabilities of the memory management system.
#+attr_latex: :width 500px
#+CAPTION: Toooba processor with pseudo code change to bypass DataTLB.
@@ -40,37 +39,41 @@ metadata storage could be used to further optimise memory allocation.
[[./diagram/Toooba-codesnippet.png]]
*** Implementation
The Figure above describes the Toooba processor with all pipelines available to provide a
highoverview of architecture and to the right side is the pseudo-code of the BlueSpec implementation
showing the change required to be done on the memory pipeline to avoid the using the Data TLB and instead
use the offset from the pointer. We will mostly focus on the memory pipleline here.
The figure [[fig:CSTOOOBA]] above illustrates the Toooba processor, showcasing all available pipelines to provide a broad overview of the architecture.
On the right-hand side, the pseudo-code of the BlueSpec\cite{bluespec} implementation highlights the modifications that will need to do to the
memory pipeline in order to bypass the use of the Data TLB and instead utilise the offset from the pointer. The primary focus will be
on the memory pipeline.\\
The design of the memory pipeline mirrors that of the other pipelines, with dispatch
and register read performing the same operations. The execute stage performs address
calculation by adding the immediate to the read register value if required, and performs
the required interactions with the Load/Store Queue and originally data TLB which is replaced with translation
encoded in the offset to do the according translations. The Load/Store
Queue is also signaled from other parts of the processor: a slot is initially requested in
the rename stage, and the memory pipeline’s finish stage has to commit the access once
all exceptions are resolved. The finish stage was originally triggered when the TLB issues a response but in
our case it's issued without walking the TLB hierarchy and intended return within a single clock cycle the translated
physical address by just adding the offset to the virtual address,
and any exceptions are handled. Crucially, the finish stage does not require the access
to have occurred for a load, giving the core its ability to process out-of-order. Memory
responses are handled asynchronously, possibly after commit, writing their data to the
relevant physical register. The memory pipeline normally remains unmodified, except to allow the new access types, data TLB bypass mechanism proposed
in the above paragraph and the required capability checks to ensure accesses are authorised.
- Each pipeline will contain a reservation station that will accept relevant instructions from the rename stage and buffer them until their register dependencies have been resolved.\\
- Following this, the dispatch stage will update the necessary state in the reservation station and forward the instruction to the rest of the pipeline.\\
- The register read stage will then latch the required values from the physical register file, or from forwarding paths if those values are already available.\\
- The execute stage will perform the specified operation. In the case of the memory pipeline, it will additionally calculate addresses by adding the immediate value to the read register where applicable, and will manage interactions with the Load/Store Queue.\\
- Originally, the memory pipeline's execute stage also interacted with the Data TLB, but this will be replaced by a translation mechanism encoded in the offset, which will perform the necessary address translations.\\
- The Load/Store Queue will continue to receive signals from various parts of the processor. A slot will be requested during the rename stage, and the memory pipeline’s finish stage will commit the access once all exceptions have been resolved.\\
- Whereas this stage was previously triggered by a TLB response, it will now operate without walking the TLB hierarchy. Instead, the physical address will be computed directly by adding the offset to the virtual address in a single clock cycle, after which any exceptions will be handled appropriately.\\
Importantly, the finish stage will not require the actual memory access to have taken place for a load instruction, enabling the core
to support out-of-order execution. Memory responses will be processed asynchronously, potentially after the commit stage, with the
returned data written to the appropriate physical register. Generally, the memory pipeline will remain unchanged, except to support
the new access types, incorporate the Data TLB bypass mechanism, and include the necessary capability checks to ensure that accesses
are properly authorised.
** Proposed evaluation
The evaluation of the proposed FAT allocator implemented using CHERI-enhanced pointers on the RISC-V Toooba architecture
aims to assess both its performance characteristics and architectural implications, particularly in the context of removing
the Translation Lookaside Buffer (TLB) from the memory access pathway. The evaluation methodology is designed to address
the research questions outlined in Section 1.2 with a focus on improvements in memory access efficiency and reductions in
latency and computational overhead.
the research questions with a focus on improvements in memory access and reductions in
latency for address translation.
*** BlueSpec simulator
To evaluate the proposed FAT pointer based memory management architecture, we conduct simulations using the
Bluespec SystemVerilog (BSV) framework. Bluespec provides a cycle-accurate hardware simulation environment that
To evaluate the proposed FAT pointer based memory management architecture, we plan to conduct simulations using the
Bluespec SystemVerilog (BSV)\cite{bsv} framework. Bluespec provides a cycle-accurate hardware simulation environment that
allows precise modelling of architectural behaviour, including custom memory pipelines, capability checking, and
physical address translation bypass mechanisms.
@@ -78,24 +81,24 @@ physical address translation bypass mechanisms.
To quantify the performance benefits of the proposed system, the following metrics will be investigated:
- *CPU clock cycles per memory access*
- *CPU clock cycles per memory access:*
This metric evaluates the computational overhead involved in memory access operations. A comparative analysis will
be conducted against conventional TLB-based systems with the hypothesis that the proposed architecture will exhibit
reduced cycle counts due to the elimination of virtual-to-physical address translation.
- *Memory access latency*
- *Memory access latency:*
The latency associated with memory access will be measured under various workload conditions. By embedding offset
information directly within pointers and bypassing the TLB, the proposed approach is expected to achieve significantly
lower latency compared to traditional systems.
- *Instruction path length*
- *Instruction path length:*
An analysis of the number of instructions executed during allocation, deallocation and memory access operations will be performed to
determine whether the additional logic required for handling FAT pointers introduces meaningful overhead.
*** System Resource Utilisation
- *Cache behaviour*
The proposed system’s influence on cache performance will be assessed through profiling tools, focusing on metrics such as cache
The proposed system's influence on cache performance will be assessed through performance counters, focusing on metrics such as cache
hit and miss rates. It is expected that physically contiguous allocations will result in improved spatial locality and cache efficiency.
- *TLB miss rate (baseline comparison)*
@@ -108,3 +111,6 @@ A series of micro and macro benchmarks will be employed to compare the FAT alloc
memory and TLBs. Micro benchmarks will include fine-grained tests of memory operations, while macro benchmarks will involve application-level
scenarios such as numerical computing and dynamic data structure manipulation, providing a comprehensive assessment of system-level impact.
\bibliographystyle{IEEEtran}
\bibliography{FuturePlan.bib}

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@@ -1,4 +1,4 @@
% Created 2025-06-18 Wed 17:52
% Created 2025-06-18 Wed 19:38
% Intended LaTeX compiler: pdflatex
\documentclass[11pt]{article}
\usepackage[utf8]{inputenc}
@@ -27,33 +27,33 @@
\tableofcontents
\section{FAT Allocator without the TLB}
\label{sec:orgb3da7db}
\label{sec:orga2b6014}
\subsection{Abstract}
\label{sec:org46fd965}
This document explores an extension of the FAT allocator approach to memory management in RISC-V Toooba.
\label{sec:orgca71060}
This document explores an extension of the FAT allocator approach to memory management in RISC-V Toooba\cite{rugg_2022}.
CHERI introduces a fine-grained memory protection mechanism by embedding bounds and permissions directly
within pointers. Leveraging this model, we propose a system in which offsets are stored within the pointer itself, enabling
direct memory access without reliance on traditional address translation mechanisms such as the TLB. This method
facilitates the design of a block-based memory allocator within physically contiguous memory. The sections expanded below
are the technique expected to be used and the evaluation criteria for the following experiment.
\subsection{Research questions}
\label{sec:orgc8884e5}
\label{sec:org7ae1821}
\begin{enumerate}
\item How can embedding offsets within a FAT pointer (i.e CHERI pointer) improve memory accesses for a block-based allocator for the RISC-V CHERI modified Toooba architecture ?
\item To what extent does eliminating TLB impact the reduction in CPU clock cycles and memory access latency in a physically contiguous memory ?
\item To what extent does eliminating TLB impact the reduction in CPU clock cycles and memory access latency ?
\end{enumerate}
\subsection{Proposed approach}
\label{sec:org4e82c7a}
\label{sec:org8425c43}
\begin{figure}[htbp]
\centering
\includegraphics[width=300px]{./diagram/MainOverview.png}
\caption{\label{fig:orgf035ab1}FAT pointer implementation with RISCV CHERI Toooba to strip the requirement of requiring a TLB.}
\caption{\label{fig:orgb6d2903}FAT pointer implementation with RISCV CHERI Toooba to strip the requirement of requiring a TLB.}
\end{figure}
FAT-Pointers based range addresses, combined with the capabilities of the CHERI architecture, introduce
bypassing the TLB hierarchy by incorporating additional metadata with memory pointers.
This enhanced architecture utilises concepts such as FlexPointer, Range Memory Mapping (RMM) to manage memory as customised sizes rather than groups
This enhanced architecture utilises concepts such as FlexPointer\cite{FlexPointer}, Range Memory Mapping (RMM)\cite{rmm} to manage memory as customised sizes rather than groups
of fixed page sizes. Range addresses play a pivotal role within this framework, defining memory regions bounded by a starting address
(Upper) and an ending address (Lower). These range addresses are encoded within FAT-pointers, allowing for precise control
over memory regions. The functionality of ranges encompasses several key aspects:
@@ -64,77 +64,82 @@ over memory regions. The functionality of ranges encompasses several key aspects
\item Instrumenting Block-Based Allocators with the FAT Pointer.
\end{itemize}
In figure 2.1, the green-highlighted section marks the unused space between the 48th and 64th bits
In figure \ref{fig:orgb6d2903}, the green-highlighted section marks the unused space between the 48th and 64th bits
within the FAT-pointer. This area of unused bits presents an opportunity to store additional metadata,
potentially enhancing the capabilities of the memory management system. Here we explore how this additional
metadata storage could be used to further optimise memory allocation.
potentially enhancing the capabilities of the memory management system.
\begin{figure}[htbp]
\centering
\includegraphics[width=500px]{./diagram/Toooba-codesnippet.png}
\caption{\label{fig:orgceb00fe}Toooba processor with pseudo code change to bypass DataTLB.}
\caption{\label{fig:org54bca80}Toooba processor with pseudo code change to bypass DataTLB.}
\end{figure}
\subsubsection{Implementation}
\label{sec:org5dc1f86}
The Figure above describes the Toooba processor with all pipelines available to provide a
highoverview of architecture and to the right side is the pseudo-code of the BlueSpec implementation
showing the change required to be done on the memory pipeline to avoid the using the Data TLB and instead
use the offset from the pointer. We will mostly focus on the memory pipleline here.
\label{sec:org51348f1}
The figure \ref{fig:org54bca80} above illustrates the Toooba processor, showcasing all available pipelines to provide a broad overview of the architecture.
On the right-hand side, the pseudo-code of the BlueSpec\cite{bluespec} implementation highlights the modifications that will need to do to the
memory pipeline in order to bypass the use of the Data TLB and instead utilise the offset from the pointer. The primary focus will be
on the memory pipeline.\\
The design of the memory pipeline mirrors that of the other pipelines, with dispatch
and register read performing the same operations. The execute stage performs address
calculation by adding the immediate to the read register value if required, and performs
the required interactions with the Load/Store Queue and originally data TLB which is replaced with translation
encoded in the offset to do the according translations. The Load/Store
Queue is also signaled from other parts of the processor: a slot is initially requested in
the rename stage, and the memory pipeline’s finish stage has to commit the access once
all exceptions are resolved. The finish stage was originally triggered when the TLB issues a response but in
our case it's issued without walking the TLB hierarchy and intended return within a single clock cycle the translated
physical address by just adding the offset to the virtual address,
and any exceptions are handled. Crucially, the finish stage does not require the access
to have occurred for a load, giving the core its ability to process out-of-order. Memory
responses are handled asynchronously, possibly after commit, writing their data to the
relevant physical register. The memory pipeline normally remains unmodified, except to allow the new access types, data TLB bypass mechanism proposed
in the above paragraph and the required capability checks to ensure accesses are authorised.
\begin{itemize}
\item Each pipeline will contain a reservation station that will accept relevant instructions from the rename stage and buffer them until their register dependencies have been resolved.\\
\item Following this, the dispatch stage will update the necessary state in the reservation station and forward the instruction to the rest of the pipeline.\\
\item The register read stage will then latch the required values from the physical register file, or from forwarding paths if those values are already available.\\
\item The execute stage will perform the specified operation. In the case of the memory pipeline, it will additionally calculate addresses by adding the immediate value to the read register where applicable, and will manage interactions with the Load/Store Queue.\\
\item Originally, the memory pipeline's execute stage also interacted with the Data TLB, but this will be replaced by a translation mechanism encoded in the offset, which will perform the necessary address translations.\\
\item The Load/Store Queue will continue to receive signals from various parts of the processor. A slot will be requested during the rename stage, and the memory pipeline’s finish stage will commit the access once all exceptions have been resolved.\\
\item Whereas this stage was previously triggered by a TLB response, it will now operate without walking the TLB hierarchy. Instead, the physical address will be computed directly by adding the offset to the virtual address in a single clock cycle, after which any exceptions will be handled appropriately.\\
\end{itemize}
Importantly, the finish stage will not require the actual memory access to have taken place for a load instruction, enabling the core
to support out-of-order execution. Memory responses will be processed asynchronously, potentially after the commit stage, with the
returned data written to the appropriate physical register. Generally, the memory pipeline will remain unchanged, except to support
the new access types, incorporate the Data TLB bypass mechanism, and include the necessary capability checks to ensure that accesses
are properly authorised.
\subsection{Proposed evaluation}
\label{sec:orgf2b6d8d}
\label{sec:orgd48ec63}
The evaluation of the proposed FAT allocator implemented using CHERI-enhanced pointers on the RISC-V Toooba architecture
aims to assess both its performance characteristics and architectural implications, particularly in the context of removing
the Translation Lookaside Buffer (TLB) from the memory access pathway. The evaluation methodology is designed to address
the research questions outlined in Section 1.2 with a focus on improvements in memory access efficiency and reductions in
latency and computational overhead.
the research questions with a focus on improvements in memory access and reductions in
latency for address translation.
\subsubsection{BlueSpec simulator}
\label{sec:org656f2ba}
To evaluate the proposed FAT pointer based memory management architecture, we conduct simulations using the
Bluespec SystemVerilog (BSV) framework. Bluespec provides a cycle-accurate hardware simulation environment that
\label{sec:org7a60e2a}
To evaluate the proposed FAT pointer based memory management architecture, we plan to conduct simulations using the
Bluespec SystemVerilog (BSV)\cite{bsv} framework. Bluespec provides a cycle-accurate hardware simulation environment that
allows precise modelling of architectural behaviour, including custom memory pipelines, capability checking, and
physical address translation bypass mechanisms.
\subsubsection{Performance Metrics}
\label{sec:org7678ffe}
\label{sec:org3ab69c0}
To quantify the performance benefits of the proposed system, the following metrics will be investigated:
\begin{itemize}
\item \textbf{CPU clock cycles per memory access}
\item \textbf{CPU clock cycles per memory access:}
This metric evaluates the computational overhead involved in memory access operations. A comparative analysis will
be conducted against conventional TLB-based systems with the hypothesis that the proposed architecture will exhibit
reduced cycle counts due to the elimination of virtual-to-physical address translation.
\item \textbf{Memory access latency}
\item \textbf{Memory access latency:}
The latency associated with memory access will be measured under various workload conditions. By embedding offset
information directly within pointers and bypassing the TLB, the proposed approach is expected to achieve significantly
lower latency compared to traditional systems.
\item \textbf{Instruction path length}
\item \textbf{Instruction path length:}
An analysis of the number of instructions executed during allocation, deallocation and memory access operations will be performed to
determine whether the additional logic required for handling FAT pointers introduces meaningful overhead.
\end{itemize}
\subsubsection{System Resource Utilisation}
\label{sec:org83b8682}
\label{sec:org2a44a34}
\begin{itemize}
\item \textbf{Cache behaviour}
The proposed system’s influence on cache performance will be assessed through profiling tools, focusing on metrics such as cache
The proposed system's influence on cache performance will be assessed through performance counters, focusing on metrics such as cache
hit and miss rates. It is expected that physically contiguous allocations will result in improved spatial locality and cache efficiency.
\item \textbf{TLB miss rate (baseline comparison)}
@@ -142,9 +147,12 @@ Although the system does not utilise a TLB, comparative analysis will be perform
the performance cost typically incurred through TLB misses, thereby contextualising the advantage of their removal.
\end{itemize}
\subsubsection{Benchmarking Against Baseline Architectures}
\label{sec:org186f134}
\label{sec:orgc282a3a}
A series of micro and macro benchmarks will be employed to compare the FAT allocator with traditional memory allocators that rely on virtual
memory and TLBs. Micro benchmarks will include fine-grained tests of memory operations, while macro benchmarks will involve application-level
scenarios such as numerical computing and dynamic data structure manipulation, providing a comprehensive assessment of system-level impact.
\bibliographystyle{IEEEtran}
\bibliography{FuturePlan.bib}
\end{document}