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Akilan Selvacoumar
2025-04-21 10:37:11 +01:00
parent ab354efb68
commit b4be6facbc
9 changed files with 179 additions and 88 deletions
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@@ -38,17 +38,19 @@
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docs/EuroSys/Paper/paper.tex
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@@ -334,25 +334,25 @@ memory address translations. A TLB is a specialised cache in the memory manageme
It reduces the time required to convert virtual addresses to physical addresses. When a program accesses
data in memory, the MMU first checks the TLB for a matching entry and avoids the slow process of
accessing the page tables situated in memory. However, as applications grow more complex, the fixed size of
TLBs often cannot keep up, leading to more TLB misses and performance slowdowns~\cite{mittal_survey_2017}.
TLBs often cannot keep up leading to more TLB misses and performance slowdowns~\cite{mittal_survey_2017}.
To tackle this issue, researchers have explored new solutions, including the use of
huge pages~\cite{panwar_hawkeye_2019}.
Huge pages, also known as large pages, allow for the allocation of memory in significantly larger chunks
Huge pages, also known as large pages allow for the allocation of memory in significantly larger chunks
compared to traditional small pages. By reducing the number of TLB entries needed to access a given amount
of memory, huge pages offer a potential avenue for optimising TLBs which are used by reducing the number
of memory. Huge pages offer a potential avenue for optimising TLBs which are used by reducing the number
of entries needed to map large memory regions. This not only decreases the frequency of
TLB misses but also lowers the overhead associated with address translation. By minimising
these bottlenecks, huge pages can improve system performance in aspects such as speeding
up memory-intensive applications, reducing latency in data access, and enhancing throughput for
up memory-intensive applications, reducing latency in data access and enhancing throughput for
workloads that rely heavily on large datasets.
Simultaneously, advancements in hardware-level security, such as the Capability Hardware Enhanced RISC Instructions (CHERI)
~\cite{woodruff_cheri_2014} architecture presents additional opportunities for performance enhancement. CHERI's capability-based addressing approach not
only strengthens system security by tightly controlling memory access but also opens avenues for optimising memory management
operations. By integrating CHERI's compressed encoded bounds~\cite{woodruff_cheri_2019} with the use of huge pages, We have shown it is possible to track and manage
large, physically contiguous memory blocks without requiring numerous TLB entries. This combination reduces the TLB pressure by minimising the number of
entries required to map extensive memory regions, thereby decreasing TLB misses and improving address translation performance.
operations. By integrating CHERI's compressed encoded bounds~\cite{woodruff_cheri_2019} with the use of huge pages, We have shown it is possible to track, manage
large and physically contiguous memory blocks without requiring numerous TLB entries. This combination reduces the TLB pressure by minimising the number of
entries required to map extensive memory regions thereby decreasing TLB misses and improving address translation performance.
Furthermore, we introduce FAT which accelerates memory-intensive tasks by reducing the overhead associated with managing non-contiguous
memory allocations. The contributions for the following paper are as follows:
\begin{itemize}
@@ -470,7 +470,7 @@ for scalable software compartmentalisation.
\subsection{CHERI CC}
CHERI Concentrate: Practical Compressed Capabilities\cite{woodruff_cheri_2019} introduces a compression scheme for CHERI that aims to address the performance and compatibility challenges associated with
capability pointers. Capability pointers enhance memory safety by embedding bounds and permissions directly
within pointers. Traditional implementations of CHERI double their size—leading in bounds to increased memory usage. CHERI CC
within pointers. Traditional implementations of CHERI double their size leading in bounds to increased memory usage. CHERI CC
proposes a compression strategy that preserves security while reducing size and inefficiencies. Key contributions include a floating-point
bound encoding technique with an internal exponent mechanism that offers greater precision for smaller objects and optimised space usage for larger ones.
@@ -517,9 +517,9 @@ in this implementation is the use of range addresses with CHERI CC~\cite{woodruf
Figure \ref{fig:HighOverviewArchitecture} illustrates a comparison between standard memory allocation (\textit{malloc()}) and the proposed FAT method. The standard approach involves a C program interacting with a custom allocator which uses 48-bit
virtual addresses and a TLB walker (L1, L2 and L3 cache) to achieve non-contiguous allocation in physical memory.
This typically results in more TLB entries and increased TLB misses increasing the reasoning to have more TLB walks.
In contrast, the FAT Address Translations method employs a custom allocator leveraging
In contrast, the FAT method employs a custom allocator leveraging
physically contiguous memory by using CHERI to encode
bounds within the pointers and as shown in the figure \ref{fig:HighOverviewArchitecture} (there is almost no reliance on walking the TLB hierarchy).
bounds within the pointers and as shown in the figure \ref{fig:HighOverviewArchitecture}. There is almost no reliance on walking the TLB hierarchy.
% Figure \ref{fig:HighOverviewArchitecture} illustrates
% the methodology employed to use the CHERI
@@ -558,7 +558,7 @@ This scenario simulates a block-based memory allocator operating within the conf
The allocations use the bounds encoded in FAT which ensures tracking of the allocated memory regions.
By using the CHERI bounds, this method maintains the contiguity of the allocated blocks within the huge page.
\subsection{128 bit compressed bounds}
\section{128 bit compressed bounds}
\label{sec:128bitCompressedBounds}
% We use CHERI CC (Compressed bounds) to track regions of memory used in physically
% contigous space. CHERI CC consists of bounds which are compressed and represent a
@@ -855,8 +855,8 @@ the proposed changes.
\end{table*}
\subsection{Benchmarks}
We elaborate here on the two classes of benchmarks~\cite{Benchmark}. Micro benchmarks (Section~\ref{sec:Micro}).
focused on particular allocation and deallocation patterns such as sequential and
We elaborate here on the two classes of benchmarks~\cite{Benchmark}. Micro benchmarks
focus on particular allocation, deallocation patterns such as sequential and
random memory accesses. This is to stress-test the allocator under controlled conditions.
Macro benchmarks involves real-world applications offering insights into how
the allocator performs with complex memory allocation demands such as large datasets with varying execution contexts.

30
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@@ -1,9 +1,10 @@
Recheck require read of the paper
- [x] Captilisation fixes (Recheck)
- [ ] Check for unessary commas (Requires read through paper) (Recheck)
- [ ] Check references (Last priority)
- [x] Unify english grammer (emphasize -> Check british english spelling) (Recheck)
** General changes
- [x] Captilisation fixes
- [x] Check for unessary commas (Requires read through paper)
- [x] Check references (Last priority)
- [x] Unify english grammer (emphasize -> Check british english spellings)
- [x] Text make to italics (For function calls)
- [x] Space missing from bracket
- [x] Utlizing to using
@@ -12,15 +13,15 @@ Recheck require read of the paper
- [x] Comment out future work section
- [x] Section with always captial S
- [x] RMM fix reference
** Literature review
** Literature review
- [x] TLB reach needs defining
- [x] PTE acronym
- [x] Citation (HP Tunable page table)
- [x] CHERI standardise bullet points into a
paragraph.
** FAT address range table
** FAT address range table
- [x] Sentence 1 remove "talks about"
- [x] "Lesser pressure" FAT leverages to reduce pressure on the TLB
- [x] Fix "as show" to "as shown"
@@ -38,16 +39,15 @@ Recheck require read of the paper
- [x] "To build up based on Section 3.1 and 3.2."
Remove this setence
- [x] "As demonstrated
384 with the allocator implementation in section 4"
- [x] "As demonstrated with the allocator implementation in section 4"
Remove this sentence
- [x] "repcrecated" to "replicated"
** Malloc implementation
** Malloc implementation
- [x] "Specifically, the start and end addresses encoded in FAT to provide the necessary information to identify the exact memory block to be deallocated."
Rewrite this sentence
** Evaluation
** Evaluation
- [x] 2nd para move to benchmarks section
- [x] "The results (section 5.3)... (comment out)
- [x] "The expirement setup" comment out
@@ -55,12 +55,6 @@ Recheck require read of the paper
- [x] "This observation highlights the importance"
Comment out
** Conclusion
** Conclusion
- [x] "This approach has helped reduce" -> "This approach reduces"
- [x] "Remove comprehensive"
** Read 1
*** Introduction
- [ ] Check if Rob mentioned paraphrasing setence 1.

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\begin{document}
\tableofcontents
Recheck require read of the paper
\section{General changes}
\label{sec:org525fa77}
\begin{itemize}
\item Captilisation fixes
\item Check for unessary commas (Requires read through paper)
\item Check references (Last priority)
\item Unify english grammer (emphasize -> Check british english spellings)
\item Text make to italics (For function calls)
\item Space missing from bracket
\item Utlizing to using
\item Small number use word
\item Make all past tense to present tense (Recheck)
\item Comment out future work section
\item Section with always captial S
\item RMM fix reference
\end{itemize}
\section{Literature review}
\label{sec:org5f6e72b}
\begin{itemize}
\item TLB reach needs defining
\item PTE acronym
\item Citation (HP Tunable page table)
\item CHERI standardise bullet points into a
paragraph.
\end{itemize}
\section{FAT address range table}
\label{sec:orgc1556d2}
\begin{itemize}
\item Sentence 1 remove "talks about"
\item "Lesser pressure" FAT leverages to reduce pressure on the TLB
\item Fix "as show" to "as shown"
\item Remove "CHERI CC [4] as referred in section 3.2."
to "CHERI CC [4] (section 3.2)"
\item Explain Cheri CC in the literature review
\item Move Cheri CC reference to it has been observed
\item "With FAT rather than using fixed size TLB entries page sizes"
Rephrase this sentence.
\item "We use CHERI CC bounds to 344 be dynamic in
size to be defined based on the size provided when
345 calling malloc. Offering a more flexible
alternative than fixed-size 346 TLB entries."
Make this into 1 sentence.
\item "To build up based on Section 3.1 and 3.2."
Remove this setence
\item "As demonstrated with the allocator implementation in section 4"
Remove this sentence
\item "repcrecated" to "replicated"
\end{itemize}
\section{Malloc implementation}
\label{sec:org8098e0d}
\begin{itemize}
\item "Specifically, the start and end addresses encoded in FAT to provide the necessary information to identify the exact memory block to be deallocated."
Rewrite this sentence
\end{itemize}
\section{Evaluation}
\label{sec:org67b48c5}
\begin{itemize}
\item 2nd para move to benchmarks section
\item "The results (section 5.3)\ldots{} (comment out)
\item "The expirement setup" comment out
\item Replace "lesser" with fewer
\item "This observation highlights the importance"
Comment out
\end{itemize}
\section{Conclusion}
\label{sec:orge940240}
\begin{itemize}
\item "This approach has helped reduce" -> "This approach reduces"
\item "Remove comprehensive"
\end{itemize}
\end{document}