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Akilan Selvacoumar
2025-04-18 14:58:37 +01:00
parent 3bc015f227
commit d46c2c8d86
10 changed files with 468 additions and 297 deletions
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32
docs/EuroSys/Paper/paper.aux
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@@ -6,23 +6,26 @@
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5
docs/EuroSys/Paper/paper.blg
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@@ -13,6 +13,7 @@ Warning--entry type for "Morello" isn't style-file defined
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(There were 18 warnings)

14
docs/EuroSys/Paper/paper.fdb_latexmk
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13
docs/EuroSys/Paper/paper.fls
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@@ -230,13 +230,21 @@
% we show that our allocator can reduce TLB misses by up to 90\%,
% leading to substantial improvements in wall clock runtimes for memory-intensive
% applications.
The increasing disparity between application workloads and the capacity of translation lookaside buffers (TLBs) has prompted researchers
to explore solutions to mitigate the extra clock cycles incurred during a TLB miss. One such approach involves leveraging physically contiguous memory
and the use of huge pages. Concurrently, advancements in hardware-level system security—exemplified by the Capability Hardware
Enhanced RISC Instructions (CHERI) architecture—offer additional opportunities for improving TLB performance. CHERI introduces
capability-based addressing, a novel approach that enhances system security by associating capabilities with memory pointers. By leveraging capability-based
addressing, we introduce a memory allocator that can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that
our allocator can reduce TLB misses by up to 90\%, leading to improvements in wall clock runtimes for memory-intensive applications.
% The increasing disparity between application workloads and the capacity of translation lookaside buffers (TLBs) has prompted researchers
% to explore solutions to mitigate the extra clock cycles incurred during a TLB miss. One such approach involves leveraging physically contiguous memory
% and the use of huge pages. Concurrently, advancements in hardware-level system security—exemplified by the Capability Hardware
% Enhanced RISC Instructions (CHERI) architecture—offer additional opportunities for improving TLB performance. CHERI introduces
% capability-based addressing, a novel approach that enhances system security by associating capabilities with memory pointers. By leveraging capability-based
% addressing, we introduce a memory allocator that can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that
% our allocator can reduce TLB misses by up to 90\%, leading to improvements in wall clock runtimes for memory-intensive applications.
The increasing gap between workload memory requirements and the capacity of translation lookaside buffers (TLBs) means TLB misses
are more frequency, costing additional clock cycles, impacting runtime performance. One solution is to use physically contiguous
memory in conjunction with huge pages. We propose an alternative approach, by exploiting capability-based addressing in the
CHERI architecture. This paper presents a new memory allocator. It associates capabilities with memory pointers. integrating
block-based allocations within huge pages. Our allocator reduces TLB misses by up to 90\%, which leads to reduced runtimes
for memory-intensive applications.
\end{abstract}
%%
@@ -377,18 +385,18 @@ high memory throughput by reducing the address translation overhead.
% and end of the segment. Any virtual address within this region
% can be translated by adding the fixed offset between the virtual
% and physical address.
Increasing TLB reach can be achieved by using larger page sizes, such as huge pages~\cite{panwar_hawkeye_2019}, which are common in modern computer systems.
Increasing TLB reach\cite{TLBReach} can be achieved by using larger page sizes, such as huge pages~\cite{panwar_hawkeye_2019}, which are common in modern computer systems.
The x86-64 architecture supports huge pages of 2 MB and 1 GB, backed by OS mechanisms like Transparent Huge Pages (THP)~\cite{THP}
and HugeTLBFS in Linux. However, available page sizes in x86-64 are limited, leading to internal fragmentation issues.
% Alternate segment technique
% - JayneelGandhi,ArkapravaBasu,MarkD.Hill,andMichaelM.Swift.2014.Efficientmemoryvirtualization:Reducing
For instance, allocating 1 MB with 4 KB base pages requires 256 PTEs, but using a 2 MB huge page would waste
For instance, allocating 1 MB with 4 KB base pages requires 256 PTEs (Page Table Entries), but using a 2 MB huge page would waste
half of the memory space. Some architectures offer more page size choices, such as Intel Itanium, which
allows different areas of the address space to have their own page sizes. Itanium uses a hash page table to organize huge
pages, but without significant changes to the conventional page table, it only helps reduce page walk overheads.
HP Tunable Base Page Size permits the OS to adjust the base page size, but still faces internal fragmentation problems,
with HP recommending a base page size of no more than 16 KB. Shadow Superpage~\cite{Shadow_superpages} introduces a new translation level
Huge page tunable base page size permits the OS to adjust the base page size, but still faces internal fragmentation problems,
with huge page recommending a base page size of no more than 16 KB. Shadow Superpage~\cite{Shadow_superpages} introduces a new translation level
in the memory controller to merge non-contiguous physical pages into a huge page in a shadow memory space, extending
TLB coverage. However, this approach requires all memory traffic to be translated again in the memory controller,
resulting in additional latency for memory accesses.
@@ -435,29 +443,46 @@ reducing the need for costly page table walks.
\subsection{CHERI}
\label{sec:orgbf2eaac}
CHERI extends conventional processor
Instruction-Set Architectures (ISAs) with architectural capabilities to enable fine-grained
memory protection and highly scalable software compartmentalization. CHERI is a hybrid
capability architecture that can combine capabilities with conventional MMU (Memory Management Unit) based systems.
The contributions of CHERI include:
\begin{itemize}
\item ISA changes to introduce architectural capabilities.
\item New microarchitecture proving that capabilities can be implemented efficiently in hardware, with support for
efficient tagged memory to protect capabilities and compress capabilities to reduce memory overhead.
\item A newly designed software construction model that uses capabilities to provide fine-grained memory protection
and scalable software compartmentalization.
\item Language and compiler extensions for using capabilities with C and C++.
\item OS extensions to support fine-grained memory protection (spatial, referential, and (non-stack) temporal memory safety)
and abstraction extensions for scalable software compartmentalization.
\end{itemize}
% CHERI extends conventional processor
% Instruction-Set Architectures (ISAs) with architectural capabilities to enable fine-grained
% memory protection and highly scalable software compartmentalization. CHERI is a hybrid
% capability architecture that can combine capabilities with conventional MMU (Memory Management Unit) based systems.
% The contributions of CHERI include:
% \begin{itemize}
% \item ISA changes to introduce architectural capabilities.
% \item New microarchitecture proving that capabilities can be implemented efficiently in hardware, with support for
% efficient tagged memory to protect capabilities and compress capabilities to reduce memory overhead.
% \item A newly designed software construction model that uses capabilities to provide fine-grained memory protection
% and scalable software compartmentalization.
% \item Language and compiler extensions for using capabilities with C and C++.
% \item OS extensions to support fine-grained memory protection (spatial, referential, and (non-stack) temporal memory safety)
% and abstraction extensions for scalable software compartmentalization.
% \end{itemize}
CHERI extends conventional processor Instruction-Set Architectures (ISAs)
with architectural capabilities to enable fine-grained memory protection
and highly scalable software compartmentalization. It is a hybrid capability
architecture that can combine capabilities with conventional MMU (Memory Management Unit)
based systems. The contributions of CHERI include ISA changes to introduce architectural
capabilities; a new microarchitecture that demonstrates capabilities can be implemented efficiently in hardware,
with support for efficient tagged memory to protect capabilities and compress them to reduce memory overhead;
a newly designed software construction model that uses capabilities to provide fine-grained memory protection and scalable
software compartmentalization; language and compiler extensions for using capabilities with C and C++; and OS extensions to
support fine-grained memory protection (including spatial, referential, and non-stack temporal memory safety) and abstraction extensions
for scalable software compartmentalization.
\subsection{CHERI CC}
CHERI Concentrate: Practical Compressed Capabilities\cite{woodruff_cheri_2019} introduces a compression scheme for CHERI, aiming to address the performance and compatibility challenges associated with
capability pointers. Capability pointers enhance memory safety by embedding bounds and permissions directly
within pointers, but traditional implementations double their size—leading to increased memory usage. CHERI CC
proposes a compression strategy that preserves security while reducing size and inefficiencies. Key contributions include a floating-point
bounds encoding technique with an internal exponent mechanism that offers greater precision for smaller objects and optimized space usage for larger ones.
\section{Fat Address Translations}
\label{sec:FatPointerTranslations}
This section talks about how Fat Address Translations(FAT) uses the CHERI architecture to
bring about block based allocations in physically contiguous memory. FAT
leverages techniques like FlexPointer~\cite{chen_flexpointer_2023} and Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to
achieve lesser pressure in the TLB. A key component
Fat Address Translations(FAT) uses the CHERI architecture to
bring about block based allocations in physically contiguous memory.
FAT leverages techniques like FlexPointer~\cite{chen_flexpointer_2023} and Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to
reduce pressure on the TLB. A key component
in this implementation is the use of range addresses with CHERI CC~\cite{woodruff_cheri_2019}.
% Fat-pointer Address Translations, combined with the capabilities of the CHERI
@@ -497,7 +522,7 @@ free virtual addresses and a TLB walk (L1, L2 and L3 cache) to achieve non-conti
This typically results in more TLB entries and increased TLB misses increasing the reasoning to have more TLB walks.
In contrast, the FAT Address Translations method employs a custom allocator leveraging
physically contiguous memory by using CHERI to encode
bounds within the pointers and as show in the figure \ref{fig:HighOverviewArchitecture} there is almost no reliance on walking the TLB hierarchy.
bounds within the pointers and as shown in the figure \ref{fig:HighOverviewArchitecture} there is almost no reliance on walking the TLB hierarchy.
% Figure \ref{fig:HighOverviewArchitecture} illustrates
% the methodology employed to use the CHERI
@@ -526,8 +551,8 @@ A memory range in FAT has 2 points to track memory in physical contiguous space
is the top and bottom. These 2 points are 2 virtual addresses and the range consists of
addresses which lie within this and refers to addresses allocated by invoking malloc.
In FAT memory ranges are established using
bounds encoded within the pointer, adhering to CHERI CC~\cite{woodruff_cheri_2019}
as referred in section ~\ref{sec:128bitCompressedBounds}.
bounds encoded within the pointer, adhering to CHERI CC~\cite{woodruff_cheri_2019}.
% as referred in section ~\ref{sec:128bitCompressedBounds}.
Figure \ref{fig:RangeOfMemory} illustrates a straightforward use-case in which the dark pink line represents a single,
large contiguous memory area, or huge page. Within this huge page, the orange and blue lines indicate
@@ -564,14 +589,18 @@ allocated.
% eliminating the need for multiple TLB entries for each allocation.
Allocators like Jemalloc typically allocate objects under
512 bytes~\cite{woodruff_cheri_2019}. When an object’s bounds cannot be precisely represented, padding is required to ensure
512 bytes. When an object’s bounds cannot be precisely represented, padding is required to ensure
memory safety. However, it has been observed that Jemalloc rarely needs more than 6 bits to store the
exponent values within compressed bounds. This means that the default behavior of allocators such as Jemalloc, would allow precise
exponent values within compressed bounds (as shown in~\cite{woodruff_cheri_2019}). This means that the default behavior of allocators such as Jemalloc, would allow precise
representation of bounds within CHERI CC.
With FAT rather than using fixed size TLB entries page sizes (such as 4KB, 2MB and 1GB pages).
We use CHERI CC bounds to be dynamic in size to be defined based on the size provided when calling
malloc. Offering a more flexible alternative than fixed-size TLB entries.
% With FAT rather than using fixed size TLB entries page sizes (such as 4KB, 2MB and 1GB pages)
% we use CHERI CC bounds to be dynamic in size to be defined based on the size provided when calling
% malloc offering a more flexible alternative than fixed-size TLB entries.
Instead of relying on fixed-size TLB entries with set page sizes (such as 4KB, 2MB, or 1GB), FAT uses CHERI
CC to define dynamic bounds based on the size requested at allocation time (e.g., during a \textit{malloc} call).
This approach offers a more flexible alternative to the traditional fixed-size TLB model.
% We use the CHERI CC
% bounds to be repurposed to encode dynamic sized addresses ranges.
@@ -591,12 +620,13 @@ malloc. Offering a more flexible alternative than fixed-size TLB entries.
\caption{FAT Address Translations using huge pages}
\label{fig:HugePages}
\end{figure}
To build up based on Section ~\ref{sec:RangeMemory} and ~\ref{sec:128bitCompressedBounds}.
% To build up based on Section ~\ref{sec:RangeMemory} and ~\ref{sec:128bitCompressedBounds}.
We are able to pre-allocate memory using huge pages and are able to mark smaller allocations
using ranges by storing them as bounds within the pointer. Each of these memory ranges can be
called as a block. Since we have numerous blocks inside a huge page we allow block based
memory patters within physically contiguous memory. As demonstrated with the allocator
implementation in section ~\ref{sec:MemoryAllocator}.
memory patters within physically contiguous memory.
% As demonstrated with the allocator
% implementation in section ~\ref{sec:MemoryAllocator}.
%Traditional address translation methods rely on hierarchical
%structures to map virtual addresses to physical addresses.
@@ -622,7 +652,7 @@ Figure \ref{fig:HugePages} illustrates a use-case of huge pages where the green
line represents a sample access to read within a contigous
space of physical memory. The dotted lines represents the
bounds for that particular pointer access. Using bounds
stored on the pointer a block based pattern can be reprecated
stored on the pointer a block based pattern can be replicated
on physically contigous memory.
\section{Memory allocator design}
@@ -682,9 +712,13 @@ efficient memory management but also demonstrates a practical usecase of huge pa
The memory deallocation (Algorithm \ref{alg:free}) mechanism in the proposed allocator is facilitated by the FAT structure
introduced in the malloc algorithm. When the free function is invoked, it uses the metadata
embedded within the FAT to determine the range and size of the allocated memory region.
Specifically, the start and end addresses encoded in FAT to provide the necessary information
to identify the exact memory block to be deallocated. This allows the allocator to unmap
the corresponding memory region from the address space.
Specifically, FAT encodes the start and end addresses of each allocation, providing the information needed to
identify the memory block to be deallocated. This enables the allocator to accurately unmap the corresponding
memory region from the address space.
% Specifically, the start and end addresses encoded in FAT to provide the necessary information
% to identify the exact memory block to be deallocated. This allows the allocator to unmap
% the corresponding memory region from the address space.
By extracting the bounds and size directly from FAT, the free function eliminates the need
for additional metadata lookups or complex data structures.
@@ -728,24 +762,24 @@ detailed aspects of the allocator's behavior. Macro benchmarks, on the other han
encompass larger, real-world C programs, allowing us to assess the allocator's
performance in more practical, real-world scenarios.
The experiment setup (section~\ref{sec:Experiment}) details the software stack used for evaluation. It includes
the specific configurations, compiler options, and system environment tailored
to benchmark the proposed allocator. This ensures consistency and repeatability
in our results, providing a solid foundation for meaningful comparisons.
% The experiment setup (section~\ref{sec:Experiment}) details the software stack used for evaluation. It includes
% the specific configurations, compiler options, and system environment tailored
% to benchmark the proposed allocator. This ensures consistency and repeatability
% in our results, providing a solid foundation for meaningful comparisons.
We further elaborated on the two classes of benchmarks executed. Micro benchmarks (section~\ref{sec:Micro}).
focused on particular allocation and deallocation patterns, such as sequential and
random memory accesses, to stress-test the allocator under controlled conditions.
Macro benchmarks (section~\ref{sec:Macro}) involved real-world applications, offering insights into how
the allocator performs with complex memory allocation demands, large datasets,
and varying execution contexts.
% We further elaborated on the two classes of benchmarks executed. Micro benchmarks (section~\ref{sec:Micro}).
% focused on particular allocation and deallocation patterns, such as sequential and
% random memory accesses, to stress-test the allocator under controlled conditions.
% Macro benchmarks (section~\ref{sec:Macro}) involved real-world applications, offering insights into how
% the allocator performs with complex memory allocation demands, large datasets,
% and varying execution contexts.
The results (section~\ref{sec:Results}) presents the outcomes of our benchmarks, highlighting key metrics
such as TLB miss rates, memory usage, and runtime performance. We observed that the
proposed allocator demonstrated significant improvements in reducing TLB misses,
leading to noticeable enhancements in runtime efficiency for both micro and macro
benchmarks. The behavior of specific allocation patterns and their impact on memory
performance is detailed, providing a nuanced understanding of the allocator's effectiveness.
% The results (section~\ref{sec:Results}) presents the outcomes of our benchmarks, highlighting key metrics
% such as TLB miss rates, memory usage, and runtime performance. We observed that the
% proposed allocator demonstrated significant improvements in reducing TLB misses,
% leading to noticeable enhancements in runtime efficiency for both micro and macro
% benchmarks. The behavior of specific allocation patterns and their impact on memory
% performance is detailed, providing a nuanced understanding of the allocator's effectiveness.
%Based on the evaluated results (section~\cite{sec:Usability}), the usability of the proposed allocator shows promise
%for applications requiring optimized memory management and reduced overhead from TLB misses.
@@ -828,6 +862,12 @@ the proposed changes.
The benchmarks~\cite{Benchmark} are classified into 2 classes:
\subsubsection{Micro benchmark}
We further elaborated on the two classes of benchmarks executed. Micro benchmarks (section~\ref{sec:Micro}).
focused on particular allocation and deallocation patterns, such as sequential and
random memory accesses, to stress-test the allocator under controlled conditions.
Macro benchmarks involved real-world applications, offering insights into how
the allocator performs with complex memory allocation demands, large datasets,
and varying execution contexts.
\label{sec:Micro}
\begin{itemize}
@@ -895,7 +935,7 @@ of its capability to handle memory more efficiently by leveraging huge pages.
\item DTLB walks: Due to most of the TLB entries getting hit at the L1 DTLB there is no need
to walk the TLB cache hierarchy. This is shown by an average of 99\% reduction in DTLB walks.
\item L1 DTLB refills: Since there are lesser DTLB walks and most reads are done at the L1 DTLB
\item L1 DTLB refills: Since there are fewer DTLB walks and most reads are done at the L1 DTLB
layer there is no need for numerous TLB refills to take place. Our benchmarks show on average
a 99\% reduction on DTLB refills.
@@ -948,12 +988,12 @@ unexpected change in performance. Additionally, the increased complexity of mana
number of clusters might introduce computational overhead that overshadows the memory allocator's
optimizations.
This observation highlights the importance of testing across a range of workload sizes and
configurations to uncover edge cases or specific scenarios where performance deviates from the
expected pattern. Understanding these anomalies can provide insights into the allocator's
behavior and guide future improvements to address such outliers. Despite the deviation at a
cluster size of 2000, the overall results reaffirm the allocator's capability to maintain
consistent performance benefits across most scenarios.
% This observation highlights the importance of testing across a range of workload sizes and
% configurations to uncover edge cases or specific scenarios where performance deviates from the
% expected pattern. Understanding these anomalies can provide insights into the allocator's
% behavior and guide future improvements to address such outliers. Despite the deviation at a
% cluster size of 2000, the overall results reaffirm the allocator's capability to maintain
% consistent performance benefits across most scenarios.
\subsection{Analysis}
\label{sec:Analysis}
@@ -975,32 +1015,32 @@ macro benchmarks is less pronounced. This suggests that its benefits are most re
applications with frequent and intensive memory operations rather than those constrained by
computation or I/O bottlenecks.
\section{Future work}
The current experimental setup on the ARM Morello board is constrained by the requirement that all memory reads must
pass through the (TLB) for address translation. This necessitates frequent TLB lookups, potentially
leading to performance bottlenecks. The planned future work aims to address this by leveraging CHERI
(Capability Hardware Enhanced RISC Instructions) extensions on the RISC-V architecture, specifically using the
Tooba implementation.
% \section{Future work}
% The current experimental setup on the ARM Morello board is constrained by the requirement that all memory reads must
% pass through the (TLB) for address translation. This necessitates frequent TLB lookups, potentially
% leading to performance bottlenecks. The planned future work aims to address this by leveraging CHERI
% (Capability Hardware Enhanced RISC Instructions) extensions on the RISC-V architecture, specifically using the
% Tooba implementation.
\subsection{Storing Offsets Directly on Pointers}
In the current ARM Morello setup, address translations rely on the TLB.
The future approach on RISC-V Tooba involves storing the offset directly within the pointer. This is possible due to CHERI's capability model, which supports fine-grained memory protection and can encode bounds within pointers.
Utilizing Bounds in CHERI for Block-Based Allocation:
% \subsection{Storing Offsets Directly on Pointers}
% In the current ARM Morello setup, address translations rely on the TLB.
% The future approach on RISC-V Tooba involves storing the offset directly within the pointer. This is possible due to CHERI's capability model, which supports fine-grained memory protection and can encode bounds within pointers.
% Utilizing Bounds in CHERI for Block-Based Allocation:
CHERI capabilities allow pointers to carry metadata about memory bounds, providing hardware-enforced memory safety.
By encoding the offset and bounds within the pointer, the system can directly access memory without needing intermediate translations via the TLB.
This enables the implementation of a block-based allocator that can efficiently manage memory allocations and deallocations within defined bounds.
Bypassing the TLB in RISC-V Tooba.
% CHERI capabilities allow pointers to carry metadata about memory bounds, providing hardware-enforced memory safety.
% By encoding the offset and bounds within the pointer, the system can directly access memory without needing intermediate translations via the TLB.
% This enables the implementation of a block-based allocator that can efficiently manage memory allocations and deallocations within defined bounds.
% Bypassing the TLB in RISC-V Tooba.
\subsection{Hardware Modifications:}
The Bluespec design of the RISC-V processor will be modified to allow certain memory operations to bypass the TLB. This means that when a pointer with encoded offset and bounds is used, the system can directly compute the physical address from the capability information.
This modification reduces the dependency on the TLB, decreasing latency and improving performance, especially for frequent memory operations.
% \subsection{Hardware Modifications:}
% The Bluespec design of the RISC-V processor will be modified to allow certain memory operations to bypass the TLB. This means that when a pointer with encoded offset and bounds is used, the system can directly compute the physical address from the capability information.
% This modification reduces the dependency on the TLB, decreasing latency and improving performance, especially for frequent memory operations.
\section{Conclusion} %Title of the Conclusion
This paper addresses the growing disparity between application workloads and the capacity of TLBs.
To mitigate this gap, we proposed leveraging physically contiguous memory with CHERI bounds to reduce TLB walks.
We designed a memory allocator which uses huge pages with CHERI CC scheme to track allocations within the
allocated huge page. This approach has helped reduce the number of TLB entries needed while using bounds
allocated huge page. This approach reduces the number of TLB entries needed while using bounds
to minimize fragmentation.
% Additionally,
% the report explores advancements in system security, particularly through the Capability Hardware Enhanced RISC Instructions (CHERI)
@@ -1008,7 +1048,7 @@ to minimize fragmentation.
% restricting access to memory regions, and thus protecting against various security threats. Importantly, these mechanisms
% can also improve the reduction of TLB walks to memory allocators by using CHERI bounds while maintaining CHERI's security guarantees.
\newline
Comprehensive benchmarking demonstrates that the allocator reduces TLB misses by up to 90\%,
The benchmarks demonstrate that the allocator reduces TLB misses by up to 90\%,
leading to substantial performance gains in memory-intensive workloads, though the improvements are less pronounced
for larger, computation-heavy applications. These results highlight the allocator's potential to advance memory management
by repurposing CHERI's capability-based model with the use of huge pages.

11
docs/EuroSys/Paper/references.bib
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@@ -21,6 +21,17 @@ abstract = {While superpages are an efficient solution to increase TLB reach, st
file = {Navarro - Practical, transparent operating system support fo.pdf:/Users/akilan/Zotero/storage/R9MSCWQX/Navarro - Practical, transparent operating system support fo.pdf:application/pdf},
}
@INPROCEEDINGS{TLBReach,
author={Pham, Binh and Bhattacharjee, Abhishek and Eckert, Yasuko and Loh, Gabriel H.},
booktitle={2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)},
title={Increasing TLB reach by exploiting clustering in page translations},
year={2014},
volume={},
number={},
pages={558-567},
keywords={Virtual private networks;Hardware;Organizations;Benchmark testing;Prefetching;Operating systems},
doi={10.1109/HPCA.2014.6835964}
@article{DirectSegment,
author = {Basu, Arkaprava and Gandhi, Jayneel and Chang, Jichuan and Hill, Mark D. and Swift, Michael M.},
title = {Efficient virtual memory for big memory servers},

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@@ -0,0 +1,60 @@
- [ ] Captilisation fixes
- [ ] Check for unessary commas
- [ ] Check references
- [ ] Unify english grammer
- [ ] Text make to italics (For function calls)
- [ ] Space missing from bracket
- [ ] Utlizing to using
- [ ] Small number use word
- [ ] Check for unusual amount of commas and
String them into a sentence
- [ ] Make all past tense to present tense
- [ ] Comment out future work section
- [ ] Section with always captial S
- [ ] RMM fix reference
** Literature review
- [x] TLB reach needs defining
- [x] PTE acronym
- [x] Citation (HP Tunable page table)
- [x] CHERI standardise bullet points into a
paragraph.
** FAT address range table
- [x] Sentence 1 remove "talks about"
- [x] "Lesser pressure" FAT leverages to reduce pressure on the TLB
- [x] Fix "as show" to "as shown"
- [x] Remove "CHERI CC [4] as referred in section 3.2."
to "CHERI CC [4] (section 3.2)"
- [x] Explain Cheri CC in the literature review
- [x] Move Cheri CC reference to it has been observed
- [x] "With FAT rather than using fixed size TLB entries page sizes"
Rephrase this sentence.
- [x] "We use CHERI CC bounds to 344 be dynamic in
size to be defined based on the size provided when
345 calling malloc. Offering a more flexible
alternative than fixed-size 346 TLB entries."
Make this into 1 sentence.
- [x] "To build up based on Section 3.1 and 3.2."
Remove this setence
- [x] "As demonstrated
384 with the allocator implementation in section 4"
Remove this sentence
- [x] "repcrecated" to "replicated"
** Malloc implementation
- [x] "Specifically, the start and end addresses encoded in FAT to provide the necessary information to identify the exact memory block to be deallocated."
Rewrite this sentence
** Evaluation
- [x] 2nd para move to benchmarks section
- [x] "The results (section 5.3)... (comment out)
- [x] "The expirement setup" comment out
- [x] Replace "lesser" with fewer
- [x] "This observation highlights the importance"
Comment out
** Conclusion
- [x] "This approach has helped reduce" -> "This approach reduces"
- [x] "Remove comprehensive"

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@@ -0,0 +1,60 @@
- [ ] Captilisation fixes
- [ ] Check for unessary commas
- [ ] Check references
- [ ] Unify english grammer
- [ ] Text make to italics (For function calls)
- [ ] Space missing from bracket
- [ ] Utlizing to using
- [ ] Small number use word
- [ ] Check for unusual amount of commas and
String them into a sentence
- [ ] Make all past tense to present tense
- [ ] Comment out future work section
- [ ] Section with always captial S
- [ ] RMM fix reference
** Literature review
- [ ] TLB reach needs defining
- [ ] PTE acronym
- [ ] Citation (HP Tunable page table)
- [x] CHERI standardise bullet points into a
paragraph.
** FAT address range table
- [x] Sentence 1 remove "talks about"
- [x] "Lesser pressure" FAT leverages to reduce pressure on the TLB
- [x] Fix "as show" to "as shown"
- [x] Remove "CHERI CC [4] as referred in section 3.2."
to "CHERI CC [4] (section 3.2)"
- [ ] Explain Cheri CC in the literature review
- [x] Move Cheri CC reference to it has been observed
- [ ] "With FAT rather than using fixed size TLB entries page sizes"
Rephrase this sentence.
- [x] "We use CHERI CC bounds to 344 be dynamic in
size to be defined based on the size provided when
345 calling malloc. Offering a more flexible
alternative than fixed-size 346 TLB entries."
Make this into 1 sentence.
- [x] "To build up based on Section 3.1 and 3.2."
Remove this setence
- [x] "As demonstrated
384 with the allocator implementation in section 4"
Remove this sentence
- [x] "repcrecated" to "replicated"
** Malloc implementation
- [ ] "Specifically, the start and end 448 addresses encoded in FAT to provide the necessary information 449 to identify the exact memory block to be deallocated."
Rewrite this sentence
** Evaluation
- [x] 2nd para move to benchmarks section
- [x] "The results (section 5.3)... (comment out)
- [x] "The expirement setup" comment out
- [x] Replace "lesser" with fewer
- [x] "This observation highlights the importance"
Comment out
** Conclusion
- [x] "This approach has helped reduce" -> "This approach reduces"
- [x] "Remove comprehensive"