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Akilan Selvacoumar
2025-05-01 18:52:10 +01:00
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docs/EuroSys/Paper/paper.aux
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@@ -52,10 +52,10 @@
\newlabel{alg:free}{{2}{4}{Free implementation}{algorithm.2}{}}
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\citation{cheribsd}
\citation{Benchmark}
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\citation{BenchmarkABI}
\citation{PerformanceCounter}
\citation{Benchmark}
\citation{singh1993}
\citation{holt1995}
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@@ -73,6 +73,7 @@
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@@ -92,10 +93,10 @@
\bibcite{chen_flexpointer_2023}{{11}{2023}{{Chen et~al.}}{{Chen, Tong, Yang, Yi, and Cheng}}}
\bibcite{jemalloc}{{12}{2006}{{Evans}}{{}}}
\bibcite{cheribsd}{{13}{}{{che}}{{}}}
\bibcite{Morello}{{14}{}{{Mor}}{{}}}
\bibcite{BenchmarkABI}{{15}{2023}{{Watson et~al.}}{{Watson, Clarke, Sewell, Woodruff, Moore, Barnes, Grisenthwaite, Stacer, Baranga, and Richardson}}}
\bibcite{PerformanceCounter}{{16}{}{{Per}}{{}}}
\bibcite{Benchmark}{{17}{}{{Ben}}{{}}}
\bibcite{Benchmark}{{14}{}{{Ben}}{{}}}
\bibcite{Morello}{{15}{}{{Mor}}{{}}}
\bibcite{BenchmarkABI}{{16}{2023}{{Watson et~al.}}{{Watson, Clarke, Sewell, Woodruff, Moore, Barnes, Grisenthwaite, Stacer, Baranga, and Richardson}}}
\bibcite{PerformanceCounter}{{17}{}{{Per}}{{}}}
\bibcite{singh1993}{{18}{1993}{{Singh}}{{}}}
\bibcite{holt1995}{{19}{1995}{{Holt and Singh}}{{}}}
\newlabel{tocindent-1}{0pt}

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@@ -128,6 +128,12 @@ Benchmark {ABI} - {CheriBSD} 23.11 new features tutorial.
\newblock URL
\url{https://www.cheribsd.org/tutorial/23.11/benchmark/index.html}.
\bibitem[Ben()]{Benchmark}
{CHERI}-allocator/benchmarks/benchmarks/{StressTestMalloc}/glibc-bench.c at
main · akilan1999/{CHERI}-allocator.
\newblock URL
\url{https://github.com/Akilan1999/CHERI-Allocator/blob/main/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c}.
\bibitem[Mor()]{Morello}
Department of computer science and technology – {CHERI}: The arm morello
board.
@@ -149,12 +155,6 @@ Robert N.~M. Watson, Jessica Clarke, Peter Sewell, Jonathan Woodruff, Simon~W.
Arm architecture reference manual for a-profile architecture.
\newblock URL \url{https://developer.arm.com/documentation/ddi0487/latest}.
\bibitem[Ben()]{Benchmark}
{CHERI}-allocator/benchmarks/benchmarks/{StressTestMalloc}/glibc-bench.c at
main · akilan1999/{CHERI}-allocator.
\newblock URL
\url{https://github.com/Akilan1999/CHERI-Allocator/blob/main/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c}.
\bibitem[Singh(1993)]{singh1993}
Jaswinder~Pal Singh.
\newblock \emph{Parallel Hierarchical N-body Methods and Their Implications for

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% addressing, we introduce a memory allocator that can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that
% our allocator can reduce TLB misses by up to 90\%, leading to improvements in wall clock runtimes for memory-intensive applications.
The increasing gap between workload memory requirements and the capacity of translation lookaside buffers (TLBs) means TLB misses
are more frequent, costing additional clock cycles and impacting runtime performance. One solution is to use physically contiguous
memory in conjunction with huge pages. We propose an alternative approach, by exploiting capability-based addressing in the
CHERI architecture. This paper presents a new memory allocator. It associates capabilities with memory pointers. Integrating
block-based allocations within huge pages. Our allocator reduces TLB misses by up to 90\%, which leads to decreasing runtimes
The increasing gap between workload memory requirements and the capacity of translation lookaside buffers (TLBs) means TLB misses
are more frequent, costing additional clock cycles and impacting runtime performance. One solution that has been explored is to use physically contiguous
memory in conjunction with huge pages. The contribution is an alternative approach by exploiting capability-based addressing in the
CHERI architecture. This paper presents a new memory allocator which associates capabilities with memory pointers by integrating
block-based allocations within huge pages. Our allocator reduces TLB misses by up to 90\%, which leads to decreasing runtime
for memory-intensive applications.
\end{abstract}
@@ -335,12 +335,12 @@ memory address translations. A TLB is a specialised cache in the memory manageme
It reduces the time required to convert virtual addresses to physical addresses. When a program accesses
data in memory, the MMU first checks the TLB for a matching entry and avoids the slow process of
accessing the page tables situated in memory. However, as applications grow more complex, the fixed size of
TLBs often cannot keep up leading to more TLB misses and performance slowdowns~\cite{mittal_survey_2017}.
TLBs often cannot keep up, leading to more TLB misses and performance slowdowns~\cite{mittal_survey_2017}.
To tackle this issue, researchers have explored new solutions, including the use of
huge pages~\cite{panwar_hawkeye_2019}.
Huge pages, also known as large pages allow for the allocation of memory in significantly larger chunks
compared to traditional small pages. By reducing the number of TLB entries needed to access a given amount
Huge pages also known as large pages allow for the allocation of memory in significantly larger chunks
compared to traditional small pages, by reducing the number of TLB entries needed to access a given amount
of memory. Huge pages offer a potential avenue for optimising TLBs which are used by reducing the number
of entries needed to map large memory regions. This not only decreases the frequency of
TLB misses but also lowers the overhead associated with address translation. By minimising
@@ -351,10 +351,10 @@ workloads that rely heavily on large datasets.
Simultaneously, advancements in hardware-level security, such as the Capability Hardware Enhanced RISC Instructions (CHERI)
~\cite{woodruff_cheri_2014} architecture presents additional opportunities for performance enhancement. CHERI's capability-based addressing approach not
only strengthens system security by tightly controlling memory access but also opens avenues for optimising memory management
operations. By integrating CHERI's compressed encoded bounds~\cite{woodruff_cheri_2019} with the use of huge pages we have shown it is possible to track, manage
operations. By integrating CHERI's compressed encoded bounds~\cite{woodruff_cheri_2019} with the use of huge pages, one of the contribution is demonstrating that it is possible to track, manage
large and physically contiguous memory blocks without requiring numerous TLB entries. This combination reduces the TLB pressure by minimising the number of
entries required to map extensive memory regions thereby decreasing TLB misses and improving address translation performance.
Furthermore, we introduce FAT which accelerates memory-intensive tasks by reducing the overhead associated with managing non-contiguous
Furthermore, this paper introduces Fat Address Translations(FAT) which accelerates memory-intensive tasks by reducing the overhead associated with managing non-contiguous
memory allocations. The contributions for the following paper are as follows:
\begin{itemize}
\item \textbf{FAT Addresses Translations}: Introduces FAT that include memory bounds, allowing
@@ -364,13 +364,13 @@ memory allocations. The contributions for the following paper are as follows:
used to optimise memory allocation by encoding memory bounds directly within pointers, reducing TLB reliance
(Section ~\ref{sec:128bitCompressedBounds}).
\item \textbf{Memory Allocation Algorithms}: Provides an algorithms for allocating, freeing
\item \textbf{Memory Allocation Algorithms}: Provides an algorithm for allocating, freeing
physically contiguous memory , and integrating huge pages with CHERI's capability-based bounds for enhanced memory management
(Section ~\ref{sec:MemoryAllocator}).
\end{itemize}
Through comprehensive evaluation including micro and macro benchmarks, we demonstrate the allocators ability
to reduce TLB misses by up to 90\% which yields in significant improvements in wall clock runtimes for memory-intensive
Through comprehensive evaluation including micro and macro benchmarks, It demonstrates the allocator's ability
to reduce TLB misses by up to 90\% which yields significant improvements in wall clock runtimes for memory-intensive
applications. While its impact on larger and computation-heavy workloads is less pronounced.
The proposed allocator shows strong potential for advancing memory management in scenarios requiring
high memory throughput by reducing the address translation overhead.
@@ -516,7 +516,7 @@ in this implementation is the use of range addresses with CHERI CC~\cite{woodruf
\end{figure*}
Figure \ref{fig:HighOverviewArchitecture} illustrates a comparison between standard memory allocation (\textit{malloc}) and the proposed FAT method. The standard approach involves a C program interacting with a custom allocator which uses 48-bit
virtual addresses and a TLB walker (L1, L2 and L3 cache) to achieve non-contiguous allocation in physical memory.
virtual addresses and the TLB hierarchy (L1, L2 and L3 cache) to achieve non-contiguous allocation in physical memory.
This typically results in more TLB entries and increased TLB misses increasing the reasoning to have more TLB walks.
In contrast, the FAT method employs a custom allocator leveraging
physically contiguous memory by using CHERI to encode
@@ -577,7 +577,7 @@ By using the CHERI bounds, this method maintains the contiguity of the allocated
% within the FAT-Pointer which can be repurposed as ranges in memory allocators with custom allocation
% sizes rather than fixed sized TLB entries.
We use CHERI CC~\cite{woodruff_cheri_2019} to track regions of memory in physically contiguous space.
FAT uses CHERI CC~\cite{woodruff_cheri_2019} to track regions of memory in physically contiguous space.
CHERI CC consists of compressed bounds that represent a 128-bit pointer within a 64-bit virtual address
system. Our approach uses the work of CHERI CC by using a single cycle to decode bounds from the
capability register and the bounds that are decoded are repurposed for tracking memory which is eagerly
@@ -619,9 +619,9 @@ This approach offers a more flexible alternative to the traditional fixed-size T
\label{fig:HugePages}
\end{figure}
% To build up based on Section ~\ref{sec:RangeMemory} and ~\ref{sec:128bitCompressedBounds}.
We are able to pre-allocate memory using huge pages and are able to mark smaller allocations
FAT is able to pre-allocate memory using huge pages and is able to mark smaller allocations
using ranges by storing them as bounds within the pointer. Each of these memory ranges can be
called a block. Since we have numerous blocks inside a huge page we allow block-based
called a block. Since there are numerous blocks inside a huge page, This allows for abbreviated block-based
memory patterns within physically contiguous memory.
% As demonstrated with the allocator
% implementation in section ~\ref{sec:MemoryAllocator}.
@@ -655,7 +655,7 @@ on physically contiguous memory.
\section{Memory allocator design}
\label{sec:MemoryAllocator}
This section presents a straightforward memory allocator designed and is implemented based on the
This section presents a straightforward memory allocator design which is implemented based on the
principles outlined in FAT (Section ~\ref{sec:FatPointerTranslations}). The allocator consists of three core functions: \textit{InitAlloc},
\textit{malloc}, and \textit{free}. The \textit{InitAlloc} function initialises the memory pool, setting up the necessary
data structures and metadata required for efficient memory management. The \textit{malloc} function is
@@ -748,11 +748,11 @@ applications and kernel-level operations.
\section{Evaluation}
\label{sec:Evaluation}
We conducted tests of the FAT memory allocator against Jemalloc~\cite{jemalloc}.
Jemalloc is the default memory allocator for CHERIBSD~\cite{cheribsd}. We evaluated
the reduction in TLB walks and misses and its impact on wall clock runtime.
Benchmarks of the FAT memory allocator against Jemalloc~\cite{jemalloc} was conducted.
Jemalloc is the default memory allocator for CHERIBSD~\cite{cheribsd}. The objective was to evaluate
the reduction of TLB walks ,misses and its impact on the wall clock runtime.
To comprehensively analyse the proposed allocator, we categorised benchmarks into
To comprehensively analyse the proposed allocator, the benchmarks~\cite{Benchmark} were categorised into
two classes which are micro and macro benchmarks. Micro benchmarks comprise smaller
C programs designed to target specific allocator patterns which enables us to evaluate
detailed aspects of the allocators behavior. Macro benchmarks, on the other hand,
@@ -808,7 +808,7 @@ failing to overwrite the C program at runtime with the intended \textit{malloc}
The second allocator was the standard OS memory allocator, which in the case of
CHERIBSD is Jemalloc.
Performance measurements were carried out using ARM performance counters~\cite{PerformanceCounter} to
Performance measurements (table ~\ref{table:ARMPerf}) were carried out using ARM performance counters~\cite{PerformanceCounter} to
ensure accurate evaluation. These counters provided detailed metrics allowing
us to compare the performance of the two allocators and assess the impact of
the proposed changes.
@@ -853,10 +853,11 @@ the proposed changes.
& during a memory read operation.) \\
\hline
\end{tabular}
\label{table:ARMPerf}
\end{table*}
\subsection{Benchmarks}
We elaborate here on the two classes of benchmarks~\cite{Benchmark}. Micro benchmarks
Elaborated here are two classes of benchmarks. Micro benchmarks
focus on particular allocation, deallocation patterns such as sequential and
random memory accesses. This is to stress-test the allocator under controlled conditions.
Macro benchmarks involves real-world applications offering insights into how
@@ -899,7 +900,7 @@ which are held tasks for performance evaluation. Configurable iterations and
timing help measure system performance to ensure correctness.
\item \texttt{BARNES}: Implements the Barnes-Hut algorithm to efficiently simulate the interactions within
an \(N\)-body system. A comprehensive overview of the Barnes-Hut method is provided by Singh in his doctoral
dissertation ~\cite{singh1993}. The implementation we benchmark extends the original method by permitting multiple
dissertation ~\cite{singh1993}. This implementation extends the original method by permitting multiple
particles to be stored within each leaf cell of the spatial decomposition, enhancing performance and scalability.
This extension is described by Holt and Singh ~\cite{holt1995}.
\end{itemize}
@@ -963,10 +964,10 @@ bottlenecked by factors such as computation or I/O rather than memory translatio
\caption{\label{fig:org8683315}Kmeans COZ benchmark executed against various cluster sizes}
\end{figure}
The K-means algorithm was executed with varying cluster sizes to evaluate the performance difference
between the FAT allocator and Jemalloc as the workload scales. This analysis
aims to understand how the allocators optimisations, particularly its ability to manage memory
more efficiently with huge pages, impact performance under different workload conditions.
The K-means algorithm was executed with varying cluster sizes as shown in figure~\ref{fig:org8683315}, to evaluate the performance difference
between the FAT allocator and Jemalloc as the workload scales. This analysis
aims to understand how the allocators optimisations, particularly its ability to manage memory
more efficiently with huge pages, impact performance under different workload conditions.
For most cluster sizes tested, the percentage difference in performance remained relatively
consistent. This indicates that the allocators efficiency scales predictably with increasing
@@ -975,7 +976,7 @@ consistent performance gain is likely due to the allocators ability to minimise
and efficiently manage memory allocations for the centroid and data point structures used in
the K-means algorithm.
However, an anomaly was observed at a cluster size of 2000, where the percentage difference
However, an anomaly was observed at a cluster size of 200k, where the percentage difference
deviated significantly from the trend. At this cluster size, the memory access patterns and allocation behavior may align in a way that
temporarily offsets the advantages of the FAT allocator. For example, the memory layout
might interact with system-level caching mechanisms or TLB behavior differently leading to an
@@ -1033,7 +1034,7 @@ applications with frequent and intensive memory operations rather than are compu
\section{Conclusion} %Title of the Conclusion
This paper addresses the growing disparity between application workloads and the capacity of TLBs.
To mitigate this gap, FAT proposed leveraging physically contiguous memory with CHERI bounds to reduce TLB walks.
We designed a memory allocator that uses huge pages with the CHERI CC scheme to track allocations within the
FAT is a memory allocator that uses huge pages with the CHERI CC scheme to track allocations within the
allocated huge page. This approach reduces the number of TLB entries needed while using bounds
to minimise fragmentation.
% Additionally,