95 lines
8.8 KiB
BibTeX
95 lines
8.8 KiB
BibTeX
@article{rugg_2022, title={Efficient spatial and temporal safety for microcontrollers and application-class processors}, url={https://www.repository.cam.ac.uk/handle/1810/353468}, DOI={10.17863/CAM.99588}, school={Apollo - University of Cambridge Repository}, author={Rugg, Peter}, year={2022}, keywords={CHERI, Hardware design, Memory safety, RISC-V} }
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@article{bluespec,
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author = {Nikhil, Rishiyur S. and Arvind},
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title = {What is Bluespec?},
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year = {2008},
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issue_date = {December 2008},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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volume = {38},
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number = {23},
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issn = {0163-5743},
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url = {https://doi.org/10.1145/1862867.1862868},
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doi = {10.1145/1862867.1862868},
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abstract = {Bluespec refers to a language and associated tools which are being used for all aspects of hardware system design . specification, synthesis, modeling, and verification. The language, BSV (Bluespec SystemVerilog), is based on a new model of computation for hardware, where all behavior is described as a set of rewrite rules, or Guarded Atomic Actions. Unlike the process/thread model of Verilog, VHDL and SystemC, or the sequential model of C/C++, all behavior of a BSV program can be understood in terms of atomic rule firings. This computational model has a long pedigree in formal specification and verification systems (e.g., Dijkstra's Guarded Commands, UNITY, TLA+, and EventB), and BSV makes it available for hardware design.},
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journal = {SIGDA Newsl.},
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month = dec,
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pages = {1},
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numpages = {1}
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}
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@incollection{bsv,
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address = {Cham},
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title = {Bluespec {SystemVerilog}},
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isbn = {978-3-319-26408-0},
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url = {https://doi.org/10.1007/978-3-319-26408-0_9},
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abstract = {Bluespec SystemVerilog (BSV) is a rule-based language, where hardware is described as object-oriented modules. Other high-level synthesis approaches try to hide the complexity of hardware (clock cycles, data movement, concurrency, etc.) under the appearance of a sequential and centralized execution. Instead, BSV exposes it to the user as an intuitive high-level metaphor. This language is a good candidate for expert hardware designers with a background on Register-Transfer Level (RTL) languages, such as Verilog or VHDL, for designers that have to develop critical hardware components, or for keeping a very tight control over the performance and the resources used. This chapter introduces the basic concepts of Bluespec SystemVerilog.},
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booktitle = {{FPGAs} for {Software} {Programmers}},
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publisher = {Springer International Publishing},
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author = {Arcas-Abella, Oriol and Sonmez, Nehir},
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editor = {Koch, Dirk and Hannig, Frank and Ziener, Daniel},
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year = {2016},
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doi = {10.1007/978-3-319-26408-0_9},
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pages = {165--172},
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}
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@article{FlexPointer,
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author = {Chen, Dongwei and Tong, Dong and Yang, Chun and Yi, Jiangfang and Cheng, Xu},
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title = {FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers},
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year = {2023},
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issue_date = {June 2023},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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volume = {20},
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number = {2},
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issn = {1544-3566},
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url = {https://doi.org/10.1145/3579854},
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doi = {10.1145/3579854},
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abstract = {Page-based virtual memory relies on TLBs to accelerate the address translation. Nowadays, the gap between application workloads and the capacity of TLB continues to grow, bringing many costly TLB misses and making the TLB a performance bottleneck. Previous studies seek to narrow the gap by exploiting the contiguity of physical pages. One promising solution is to group pages that are both virtually and physically contiguous into a memory range. Recording range translations can greatly increase the TLB reach, but ranges are also hard to index because they have arbitrary bounds. The processor has to compare against all the boundaries to determine which range an address falls in, which restricts the usage of memory ranges. In this article, we propose a tagged-pointer-based scheme, FlexPointer, to solve the range indexing problem. The core insight of FlexPointer is that large memory objects are rare, so we can create memory ranges based on such objects and assign each of them a unique ID. With the range ID integrated into pointers, we can index the range TLB with IDs and greatly simplify its structure. Moreover, because the ID is stored in the unused bits of a pointer and is not manipulated by the address generation, we can shift the range lookup to an earlier stage, working in parallel with the address generation. According to our trace-based simulation results, FlexPointer can reduce nearly all the L1 TLB misses, and page walks for a variety of memory-intensive workloads. Compared with a 4K-page baseline system, FlexPointer shows a 14\% performance improvement on average and up to 2.8x speedup in the best case. For other workloads, FlexPointer shows no performance degradation.},
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journal = {ACM Trans. Archit. Code Optim.},
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month = mar,
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articleno = {30},
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numpages = {24},
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keywords = {address translation, TLB reach, Tagged pointer}
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}
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@article{10.1145/2872887.2749471,
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author = {Karakostas, Vasileios and Gandhi, Jayneel and Ayar, Furkan and Cristal, Adri\'{a}n and Hill, Mark D. and McKinley, Kathryn S. and Nemirovsky, Mario and Swift, Michael M. and \"{U}nsal, Osman},
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title = {Redundant memory mappings for fast access to large memories},
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year = {2015},
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issue_date = {June 2015},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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volume = {43},
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number = {3S},
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issn = {0163-5964},
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url = {https://doi.org/10.1145/2872887.2749471},
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doi = {10.1145/2872887.2749471},
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abstract = {Page-based virtual memory improves programmer productivity, security, and memory utilization, but incurs performance overheads due to costly page table walks after TLB misses. This overhead can reach 50\% for modern workloads that access increasingly vast memory with stagnating TLB sizes.To reduce the overhead of virtual memory, this paper proposes Redundant Memory Mappings (RMM), which leverage ranges of pages and provides an efficient, alternative representation of many virtual-to-physical mappings. We define a range be a subset of process's pages that are virtually and physically contiguous. RMM translates each range with a single range table entry, enabling a modest number of entries to translate most of the process's address space. RMM operates in parallel with standard paging and uses a software range table and hardware range TLB with arbitrarily large reach. We modify the operating system to automatically detect ranges and to increase their likelihood with eager page allocation. RMM is thus transparent to applications.We prototype RMM software in Linux and emulate the hardware. RMM performs substantially better than paging alone and huge pages, and improves a wider variety of workloads than direct segments (one range per program), reducing the overhead of virtual memory to less than 1\% on average.},
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journal = {SIGARCH Comput. Archit. News},
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month = jun,
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pages = {66–78},
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numpages = {13}
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}
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@inproceedings{rmm,
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author = {Karakostas, Vasileios and Gandhi, Jayneel and Ayar, Furkan and Cristal, Adri\'{a}n and Hill, Mark D. and McKinley, Kathryn S. and Nemirovsky, Mario and Swift, Michael M. and \"{U}nsal, Osman},
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title = {Redundant memory mappings for fast access to large memories},
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year = {2015},
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isbn = {9781450334020},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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url = {https://doi.org/10.1145/2749469.2749471},
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doi = {10.1145/2749469.2749471},
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abstract = {Page-based virtual memory improves programmer productivity, security, and memory utilization, but incurs performance overheads due to costly page table walks after TLB misses. This overhead can reach 50\% for modern workloads that access increasingly vast memory with stagnating TLB sizes.To reduce the overhead of virtual memory, this paper proposes Redundant Memory Mappings (RMM), which leverage ranges of pages and provides an efficient, alternative representation of many virtual-to-physical mappings. We define a range be a subset of process's pages that are virtually and physically contiguous. RMM translates each range with a single range table entry, enabling a modest number of entries to translate most of the process's address space. RMM operates in parallel with standard paging and uses a software range table and hardware range TLB with arbitrarily large reach. We modify the operating system to automatically detect ranges and to increase their likelihood with eager page allocation. RMM is thus transparent to applications.We prototype RMM software in Linux and emulate the hardware. RMM performs substantially better than paging alone and huge pages, and improves a wider variety of workloads than direct segments (one range per program), reducing the overhead of virtual memory to less than 1\% on average.},
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booktitle = {Proceedings of the 42nd Annual International Symposium on Computer Architecture},
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pages = {66–78},
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numpages = {13},
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location = {Portland, Oregon},
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series = {ISCA '15}
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}
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