An attempt at wiring up the specUpdate interface for the Btb.

src_Core/CPU/Core.bsv

@@ -353,9 +353,11 @@ module mkCore#(CoreId coreId)(Core);
         end
         GlobalSpecUpdate#(CorrectSpecPortNum, ConflictWrongSpecPortNum) globalSpecUpdate <- mkGlobalSpecUpdate(
             joinSpeculationUpdate(
-                append(append(append(vec(regRenamingTable.specUpdate,
+                append(append(append(vec(fetchStage.specUpdate,
+                                         regRenamingTable.specUpdate,
                                          specTagManager.specUpdate,
-                                         fix.memExeIfc.specUpdate), aluSpecUpdate), fpuMulDivSpecUpdate), btqSpecUpdate)
+                                         fix.memExeIfc.specUpdate),
+                aluSpecUpdate), btqSpecUpdate), fpuMulDivSpecUpdate)
             ),
             rob.specUpdate
         );

src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv

@@ -57,6 +57,7 @@ import CCTypes::*;
 import DefaultValue::*;
 import Ras::*;
 import EpochManager::*;
+import HasSpecBits::*;
 import Performance::*;
 import Vector::*;
 import Assert::*;
@@ -155,6 +156,9 @@ interface FetchStage;
 
     // performance
     interface Perf#(DecStagePerfType) perf;
+
+    // speculation update
+    interface SpeculationUpdate specUpdate;
 `ifdef PERFORMANCE_MONITORING
     method Bool redirect_evt;
 `endif
@@ -1015,6 +1019,15 @@ module mkFetchStage(FetchStage);
 `endif
     endinterface
 
+    interface SpeculationUpdate specUpdate;
+        method Action correctSpeculation(SpecBits sb);
+            nextAddrPred.specUpdate.correctSpeculation(sb);
+        endmethod
+        method Action incorrectSpeculation(Bool kill_all, SpecTag specTag);
+            nextAddrPred.specUpdate.incorrectSpeculation(kill_all, specTag);
+        endmethod
+    endinterface
+
 `ifdef PERFORMANCE_MONITORING
     method Bool redirect_evt = redirect_evt_reg._read;
 `endif

src_Core/RISCY_OOO/procs/lib/Btb.bsv

@@ -43,6 +43,7 @@ import Vector::*;
 import CHERICC_Fat::*;
 import CHERICap::*;
 import SpecFifo::*;
+import HasSpecBits::*;
 
 export NextAddrPred(..);
 export mkBtb;
@@ -51,6 +52,7 @@ interface NextAddrPred#(numeric type hashSz);
     method Action put_pc(CapMem pc);
     interface Vector#(SupSizeX2, Maybe#(CapMem)) pred;
     method Action update(CapMem pc, CapMem brTarget, Bool taken, SpecBits specBits);
+    interface SpeculationUpdate specUpdate;
     // security
     method Action flush;
     method Bool flush_done;
@@ -169,6 +171,8 @@ module mkBtbCore(NextAddrPred#(hashSz))
         updateQ.enq(ToSpecFifo {spec_bits: specBits, data: BtbUpdate {pc: pc, nextPc: nextPc, taken: taken}});
     endmethod
 
+    interface SpeculationUpdate specUpdate = updateQ.specUpdate;
+
 `ifdef SECURITY
     method Action flush method Action flush;
         for (Integer i = 0; i < valueOf(SupSizeX2); i = i + 1) begin