Move RVFI toggle into Include_RISCY_Config.mk
Previously, Makefiles had to add new include paths and -D defines manually when they wanted to include RVFI. This caused hard-to-diagnose errors in repositories consuming Toooba that expected -D RVFI to work. This commit makes Include_RISCY_Config.mk take an optional make-variable argument RVFI, which defaults to "false", and adds the relevant paths and -D defines if it is set to "true". This does not cover RVFI_DII, which is a simulation-only extension to allow instruction injection. This commit also includes fixes to the Makefiles in ./builds/ to use this interface properly.
This commit is contained in:
Samuel Stark
committed by
Samuel Stark
Samuel Stark
parent
7e1c9fdc98
commit
02ee2bdee0
@@ -3,7 +3,7 @@
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# ================================================================
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# Path to RISCY-OOO sources not included in Common
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EXTRA_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/BSV-RVFI-DII
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EXTRA_DIRS = $(RISCY_HOME)/../../src_Verifier
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# ================================================================
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@@ -13,27 +13,31 @@ ARCH ?= RV64ACDFIMSUxCHERI
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# ================================================================
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# RISC-V config macros passed into Bluespec 'bsc' compiler
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# "-D RVFI" is set by Include_RISCY_Config
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# "-D RVFI_DII" enables injecting insructions, not just logging them,
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# and requires the EXTRA_DIRS set above
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BSC_COMPILATION_FLAGS += \
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-D RVFI_DII \
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-D RVFI \
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-D CONTRACTS_VERIFY \
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# Default ISA test
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TEST ?= rv64ui-p-add
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#================================================================
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# Parameter settings for MIT RISCY, setup paths etc. for Include_Common
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CACHE_SIZE ?= TEST
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RVFI = true
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include $(REPO)/builds/Resources/Include_RISCY_Config.mk
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#================================================================
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# Common boilerplate rules
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include $(REPO)/builds/Resources/Include_Common.mk
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#================================================================
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# Parameter settings for MIT RISCY
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CACHE_SIZE ?= TEST
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include $(REPO)/builds/Resources/Include_RISCY_Config.mk
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#================================================================
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# Makefile rules for building for specific simulator: bluesim
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@@ -3,7 +3,7 @@
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# ================================================================
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# Path to RISCY-OOO sources not included in Common
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EXTRA_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/BSV-RVFI-DII
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EXTRA_DIRS = $(RISCY_HOME)/../../src_Verifier
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# ================================================================
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@@ -13,26 +13,30 @@ ARCH ?= RV64ACDFIMSUxCHERI
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# ================================================================
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# RISC-V config macros passed into Bluespec 'bsc' compiler
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# "-D RVFI" is set by Include_RISCY_Config
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# "-D RVFI_DII" enables injecting insructions, not just logging them,
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# and requires the EXTRA_DIRS set above
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BSC_COMPILATION_FLAGS += \
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-D RVFI_DII \
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-D RVFI \
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# Default ISA test
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TEST ?= rv64ui-p-add
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#================================================================
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# Parameter settings for MIT RISCY, setup paths etc. for Include_Common
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CACHE_SIZE ?= TEST
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RVFI = true
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include $(REPO)/builds/Resources/Include_RISCY_Config.mk
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#================================================================
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# Common boilerplate rules
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include $(REPO)/builds/Resources/Include_Common.mk
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#================================================================
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# Parameter settings for MIT RISCY
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CACHE_SIZE ?= TEST
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include $(REPO)/builds/Resources/Include_RISCY_Config.mk
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#================================================================
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# Makefile rules for building for specific simulator: verilator
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@@ -3,11 +3,6 @@
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REPO ?= ../..
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ARCH ?= RV64ACDFIMSUxCHERI
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# ================================================================
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# Path to RISCY-OOO sources not included in Common
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EXTRA_DIRS = $(REPO)/src_Verifier:$(REPO)/src_Verifier/BSV-RVFI-DII
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# ================================================================
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# RISC-V config macros passed into Bluespec 'bsc' compiler
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@@ -16,7 +11,7 @@ EXTRA_DIRS = $(REPO)/src_Verifier:$(REPO)/src_Verifier/BSV-RVFI-DII
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TEST ?= rv64ui-p-add
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#================================================================
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# Parameter settings for MIT RISCY
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# Parameter settings for MIT RISCY, setup paths etc. for Include_Common
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include $(REPO)/builds/Resources/Include_RISCY_Config.mk
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@@ -10,16 +10,16 @@ ARCH ?= RV64ACDFIMSUxCHERI
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TEST ?= rv64ui-p-add
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#================================================================
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# Parameter settings for MIT RISCY, setup paths etc. for Include_Common
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include $(REPO)/builds/Resources/Include_RISCY_Config.mk
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#================================================================
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# Common boilerplate rules
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include $(REPO)/builds/Resources/Include_Common.mk
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#================================================================
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# Parameter settings for MIT RISCY
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include $(REPO)/builds/Resources/Include_RISCY_Config.mk
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#================================================================
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# Makefile rules for building for specific simulator: verilator
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@@ -62,7 +62,7 @@ BSC_COMPILATION_FLAGS += \
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-promote-warnings T0054 \
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+RTS -K128M -RTS -show-range-conflict -show-schedule
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# -D NO_SPEC_TRAINING -D NO_SPEC_REDIRECT -D NO_SPEC_STRAIGHT_PATH -D SPEC_RSB_FIXUP -D NO_SPEC_RSB_PUSH -D NO_SPEC_STL -D RVFI
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# -D NO_SPEC_TRAINING -D NO_SPEC_REDIRECT -D NO_SPEC_STRAIGHT_PATH -D SPEC_RSB_FIXUP -D NO_SPEC_RSB_PUSH -D NO_SPEC_STL
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# ================================================================
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# Runs simulation executable on ELF given by EXAMPLE
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@@ -18,6 +18,14 @@ SIM_DRAM_TYPE := AWSF1
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# use Xilinx FPU IP cores
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USE_XILINX_FPU ?= false
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# default to not including RVFI at all.
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# setting this to true enables debug-displaying of executed instructions using the RVFI trace format. See Core.bsv.
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RVFI ?= false
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# Adding "-D RVFI_DII", linking $(CORE_DIR)/src_Verifier/BSV-RVFI-DII/SocketPacketUtils/socket_packet_utils.c
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# into simulation, and adding $(CORE_DIR)/src_Verifier to the include path allows injecting instructions
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# *and* retrieving those RVFI traces over a socket, which is used for TestRIG. See <https://github.com/CTSRD-CHERI/TestRIG/blob/master/RVFI-DII.md>.
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# See the builds/*_RVFI_DII_*/ Makefiles.
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# default 1 core
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CORE_NUM ?= 1
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# TSO or WEAK
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@@ -119,7 +127,7 @@ BSC_COMPILATION_FLAGS += \
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# -D NO_LOAD_RESP_E
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# various SECURITY related flags
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# -D PERF_COUNT -D CHECK_DEADLOCK -D RENAME_DEBUG ...
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# -D NO_SPEC_RSB_PUSH -D NO_SPEC_STL -D RVFI
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# -D NO_SPEC_RSB_PUSH -D NO_SPEC_STL
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# +RTS -K1G -RTS " --bscflags=" -steps-max-intervals 200 -check-assert
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@@ -145,5 +153,10 @@ BSC_CONTRIB_LIB_DIR = %/Libraries
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endif
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BSC_CONTRIB_DIRS = $(BSC_CONTRIB_LIB_DIR)/Bus
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BSVPATH = +:$(BSC_CONTRIB_DIRS):$(WINDCORE_IFC_DIR):$(RISCV_HPM_EVENTS_DIR):$(CHERICAPLIB_DIR):$(TAG_CONTROLLER_DIRS):$(COREW_DIRS):$(BLUESTUFF_DIRS)
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BSC_PATH = -p $(BSVPATH)
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BSC_PATH += -p +:$(BSC_CONTRIB_DIRS):$(WINDCORE_IFC_DIR):$(RISCV_HPM_EVENTS_DIR):$(CHERICAPLIB_DIR):$(TAG_CONTROLLER_DIRS):$(COREW_DIRS):$(BLUESTUFF_DIRS)
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ifeq ($(RVFI),true)
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BSC_COMPILATION_FLAGS += \
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-D RVFI
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BSC_PATH += -p +:$(CORE_DIR)/src_Verifier/BSV-RVFI-DII
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endif
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@@ -15,8 +15,6 @@ build_dir:
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ifeq (,$(filter clean full_clean,$(MAKECMDGOALS)))
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include .depends.mk
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# BSC_COMPILATION_FLAGS += -D RVFI
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.depends.mk: TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv | build_dir
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if ! bluetcl -exec makedepend -elab -sim $(TMP_DIRS) $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi
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endif
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@@ -40,8 +38,8 @@ BSC_C_FLAGS += \
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-Xl -v \
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-Xc -O1 -Xc++ -O1 \
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BSC_COMPILATION_FLAGS += \
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-D RVFI
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# socket_packet_utils.c is only necessary if RVFI_DII is defined, as it's the bridge that allows
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# RVFI injection/trace retrieval, but we can compile+link it no matter what.
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# For Bluespec_2019.05.beta2-debian9stretch-amd64
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# you may have to remove the line: -Xc++ -D_GLIBCXX_USE_CXX11_ABI=0
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@@ -19,19 +19,19 @@ ifeq (,$(filter clean full_clean,$(MAKECMDGOALS)))
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include .depends.mk
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.depends.mk: TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv | build_dir Verilog_RTL
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if ! bluetcl -exec makedepend -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi
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if ! bluetcl -exec makedepend -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi
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endif
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%.bo:
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$(info building $@)
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bsc -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
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bsc -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) $(BSC_PATH) $<
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.PHONY: compile
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compile: build_dir/Top_HW_Side.bo | build_dir Verilog_RTL
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#Verilog_RTL/mkTop_HW_Side.v: build_dir Verilog_RTL /tmp/src_dir $(VERILOG_SUB_MODULES)
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#Verilog_RTL/mkTop_HW_Side.v: $(TOPFILE) build_dir/Top_HW_Side.bo build_dir Verilog_RTL
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# @echo "INFO: Verilog RTL generation ..."
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# bsc -u -verilog $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
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# bsc -u -verilog $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) $(BSC_PATH) $<
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# @echo "INFO: Verilog RTL generation finished"
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# ================================================================
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@@ -63,6 +63,9 @@ VERILATOR_FLAGS += -Wfuture-DEPRECATED
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VTOP = V$(TOPMODULE)_edited
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VERILATOR_RESOURCES = $(REPO)/builds/Resources/Verilator_resources
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# socket_packet_utils.c is only necessary if RVFI_DII is defined, as it's the bridge that allows
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# RVFI injection/trace retrieval, but we can compile+link it no matter what.
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.PHONY: simulator
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simulator: build_dir/Top_HW_Side.bo
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@echo "INFO: Verilating Verilog files (in newly created obj_dir)"
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