Fix for RVFI_DII build.

src_Core/Core/CoreW.bsv

@@ -133,23 +133,39 @@ typedef WindCoreMid #( // AXI lite subordinate control port parameters
                      , t_n_irq) CoreW_IFC #(numeric type t_n_irq);
 
 //(* synthesize *)
+`ifdef RVFI_DII
+module mkCoreW (Tuple2#(Toooba_RVFI_DII_Server, CoreW_IFC #(t_n_irq)));
+`else
 module mkCoreW (CoreW_IFC #(t_n_irq));
+`endif
    Clock clk <- exposeCurrentClock;
    Reset rst <- exposeCurrentReset;
    let newRst <- mkReset (0, True, clk, reset_by rst);
-   match {.otherRst, .ifc} <- mkCoreW_reset ( rst
-                                            , reset_by newRst.new_rst);
+   match {.otherRst
+`ifdef RVFI_DII
+          , .rvfi
+`endif
+          , .ifc} 
+     <- mkCoreW_reset ( rst, reset_by newRst.new_rst);
    rule rl_forward_debug_reset (otherRst);
       newRst.assertReset;
    endrule
+`ifdef RVFI_DII
+   return tuple2(rvfi, ifc);
+`else
    return ifc;
+`endif
 endmodule
 
 // The interface to this module is a convenience to avoid exposing the reset
 // hacks to the nicer outer interface, and not have to use a large amount of
 // reset_by to decouple the debug module from the rest...
 module mkCoreW_reset #(Reset porReset)
+`ifdef RVFI_DII
+                      (Tuple3#(PulseWire, Toooba_RVFI_DII_Server, CoreW_IFC #(t_n_irq)));
+`else
                       (Tuple2#(PulseWire, CoreW_IFC #(t_n_irq)));
+`endif
 
    // ================================================================
    // Notes on 'reset'
@@ -609,10 +625,6 @@ module mkCoreW_reset #(Reset porReset)
    endinterface;
 
 /*
-`ifdef RVFI_DII
-   interface Toooba_RVFI_DII_Server rvfi_dii_server = proc.rvfi_dii_server;
-`endif
-
 `ifdef INCLUDE_TANDEM_VERIF
    // ----------------------------------------------------------------
    // Optional TV interface
@@ -626,7 +638,7 @@ module mkCoreW_reset #(Reset porReset)
 `endif
 */
 
-   return tuple2 (innerReset, ifc);
+   return tuple3 (innerReset, proc.rvfi_dii_server, ifc);
 endmodule: mkCoreW_reset
 
 // ================================================================

src_Testbench/SoC/SoC_Top.bsv

@@ -143,7 +143,12 @@ module mkSoC_Top #(Reset dm_power_on_reset)
    // Core: CPU + Near_Mem_IO (CLINT) + PLIC + Debug module (optional) + TV (optional)
    // The Debug Module has its own RST_N reset signal (which comes
    // from outside this module as a paramter)
-   CoreW_IFC #(N_External_Interrupt_Sources)  corew <- mkCoreW;
+`ifdef RVFI_DII
+   match {.core_rvfi_dii_server , .coreifc} <- mkCoreW;
+   CoreW_IFC #(N_External_Interrupt_Sources) corew = coreifc;
+`else
+   CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW;
+`endif
 
    // SoC Boot ROM
    Boot_ROM_IFC  boot_rom <- mkBoot_ROM;
@@ -318,7 +323,7 @@ module mkSoC_Top #(Reset dm_power_on_reset)
    // To tandem verifier
    interface tv_verifier_info_get = corew.tv_verifier_info_get;
 `elsif RVFI_DII
-   interface rvfi_dii_server = corew.rvfi_dii_server;
+   interface rvfi_dii_server = core_rvfi_dii_server;
 `endif
 
    // External real memory