Some more tagsparam makefile fixes

.gitignore

@@ -20,3 +20,4 @@ builds/RV*/Verilog_RTL
 .depends.mk
 src_SSITH_P3/Verilog_RTL
 src_SSITH_P3/Verilog_RTL_sim
+**/TagTableStructure.bsv

builds/Resources/Include_Common.mk

@@ -99,9 +99,10 @@ CAPSIZE = 128
 TAGS_STRUCT = 0 64
 TAGS_ALIGN = 32
 .PHONY: tagsparams
-tagsparams: $(REPO)/libs/TagController/tagsparams.py
+tagsparams: TagTableStructure.bsv
+TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py
 	@echo "INFO: Re-generating CHERI tag controller parameters"
-	$^ -v -c $(CAPSIZE) -s $(TAGS_STRUCT:"%"=%) -a $(TAGS_ALIGN) --covered-start-addr 0x80000000 --covered-mem-size 0x3fffc000 --top-addr 0xbffff000 -b TagTableStructure.bsv
+	$^ -v -c $(CAPSIZE) -s $(TAGS_STRUCT:"%"=%) -a $(TAGS_ALIGN) --covered-start-addr 0x80000000 --covered-mem-size 0x3fffc000 --top-addr 0xbffff000 -b $@
 	@echo "INFO: Re-generated CHERI tag controller parameters"
 compile: tagsparams
 
@@ -115,7 +116,6 @@ clean:
 .PHONY: full_clean
 full_clean: clean
 	rm -r -f  $(SIM_EXE_FILE)*  *.log  *.vcd  *.hex  Logs/
-	rm -f .depends.mk
-	touch TagTableStructure.bsv
+	rm -f TagTableStructure.bsv .depends.mk
 
 # ================================================================

builds/Resources/Include_bluesim.mk

@@ -15,7 +15,7 @@ build_dir:
 ifeq (,$(filter clean full_clean,$(MAKECMDGOALS)))
 include .depends.mk
 
-.depends.mk: | build_dir
+.depends.mk: TagTableStructure.bsv | build_dir
 	if ! bluetcl -exec makedepend -elab -sim  $(TMP_DIRS)  $(RTL_GEN_DIRS)  $(BSC_COMPILATION_FLAGS)  -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi
 endif
 

src_SSITH_P3/Makefile

@@ -6,6 +6,7 @@
 help:
 	@echo '    make  compile      Recompile Core (CPU, caches) into Verilog_RTL'
 	@echo '                           NOTE: needs Bluespec bsc compiler'
+	@echo '    make  tagsparams   Generates the CHERI tag controller parameters source file'
 	@echo ''
 	@echo '    make  clean        Remove intermediate build-files'
 	@echo '    make  full_clean   Restore this directory to pristine state'
@@ -96,6 +97,20 @@ BSC_COMPILATION_FLAGS += \
 	-steps-max-intervals 10000000 \
 	-steps-warn-interval 1000000
 
+# ================================================================
+# Generate Bluespec CHERI tag controller source file
+CAPSIZE = 128
+TAGS_STRUCT = 0 64
+TAGS_ALIGN = 32
+.PHONY: tagsparams
+tagsparams: src_BSV/TagTableStructure.bsv
+src_BSV/TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py
+	@echo "INFO: Re-generating CHERI tag controller parameters"
+	$^ -v -c $(CAPSIZE) -s $(TAGS_STRUCT:"%"=%) -a $(TAGS_ALIGN) --covered-start-addr 0xc0000000 --covered-mem-size 0xbfff8000 --top-addr 0x17ffff000 -b $@
+	@echo "INFO: Re-generated CHERI tag controller parameters"
+compile_sim: tagsparams
+compile_synth: tagsparams
+
 # ================================================================
 # Generate Verilog RTL from BSV sources (needs Bluespec 'bsc' compiler)
 
@@ -129,7 +144,7 @@ compile_sim: | build_dir_sim Verilog_RTL_sim
 
 .PHONY: clean
 clean:
-	rm -r -f  *~  Makefile_*  build_dir_sim build_dir_synth
+	rm -r -f  *~  Makefile_*  build_dir_sim build_dir_synth src_BSV/TagTableStructure.bsv
 
 .PHONY: full_clean
 full_clean: clean

src_SSITH_P3/src_BSV/TagTableStructure.bsv

@@ -1,34 +0,0 @@
-/*-
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * @BERI_LICENSE_HEADER_START@
- *
- * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
- * license agreements.  See the NOTICE file distributed with this work for
- * additional information regarding copyright ownership.  BERI licenses this
- * file to you under the BERI Hardware-Software License, Version 1.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at:
- *
- *   http://www.beri-open-systems.org/legal/license-1-0.txt
- *
- * Unless required by applicable law or agreed to in writing, Work distributed
- * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
- * CONDITIONS OF ANY KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations under the License.
- *
- * @BERI_LICENSE_HEADER_END@
- */
-
-// This file was generated by the tagsparams.py script
-// 2020-03-24 15:49:40.494187
-
-import Vector::*;
-Vector#(2, Integer) tableStructure = cons(0, cons(64, nil));
-Integer table_end_addr = 'h17ffff000;
-Integer table_start_addr = 'h17e79f100;
-Integer covered_start_addr = 'hc0000000;
-Integer covered_mem_size  = 'hbfff8000;