Merge pull request #7 from jrtc27/bluesim

Add RV64ACDFIMSU_Toooba_bluesim build

builds/RV64ACDFIMSU_Toooba_bluesim/Makefile

@@ -0,0 +1,55 @@
+###  -*-Makefile-*-
+
+# ================================================================
+# Path to RISCY-OOO sources
+
+RISCY_HOME ?= ../../src_Core/RISCY_OOO
+# RISCY_HOME ?= $(HOME)/Projects/RISCV/MIT-riscy/riscy-OOO
+
+RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)/coherence/src:$(RISCY_HOME)/fpgautils/lib
+
+CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv
+
+# ALL_RISCY_DIRS = $(RISCY_DIRS)
+ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS)
+
+# ================================================================
+
+REPO ?= ../..
+ARCH ?= RV64ACDFIMSU
+
+# ================================================================
+# RISC-V config macros passed into Bluespec 'bsc' compiler
+
+BSC_COMPILATION_FLAGS += \
+	-D RV64 \
+	-D ISA_PRIV_M  -D ISA_PRIV_U  -D ISA_PRIV_S  \
+	-D SV39  \
+	-D ISA_I  -D ISA_M  -D ISA_A  -D ISA_F  -D ISA_D  -D ISA_FD_DIV  -D ISA_C  \
+	-D SHIFT_BARREL    \
+	-D MULT_SYNTH    \
+	-D Near_Mem_Caches    \
+	-D FABRIC64    \
+
+
+# Default ISA test
+
+TEST ?= rv64ui-p-add
+
+#================================================================
+# Parameter settings for MIT RISCY
+
+BSC_COMPILATION_FLAGS += -D BSIM \
+
+
+include $(REPO)/builds/Resources/Include_RISCY_Config.mk
+
+#================================================================
+# Common boilerplate rules
+
+include $(REPO)/builds/Resources/Include_Common.mk
+
+#================================================================
+# Makefile rules for building for specific simulator: bluesim
+
+include $(REPO)/builds/Resources/Include_bluesim.mk

builds/Resources/Include_bluesim.mk

@@ -0,0 +1,41 @@
+###  -*-Makefile-*-
+
+# Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved
+
+# This file is not a standalone Makefile, but 'include'd by other Makefiles
+
+# ================================================================
+# Compile Bluesim intermediate files from BSV sources (needs Bluespec 'bsc' compiler)
+
+TMP_DIRS  = -bdir build_dir  -simdir build_dir  -info-dir build_dir
+
+build_dir:
+	mkdir -p $@
+
+.PHONY: compile
+compile: build_dir
+	@echo "INFO: Re-compiling Core (CPU, Caches)"
+	bsc -u -elab -sim  $(TMP_DIRS)  $(BSC_COMPILATION_FLAGS)  $(BSC_PATH)  $(TOPFILE)
+	@echo "INFO: Re-compiled  Core (CPU, Caches)"
+
+# ================================================================
+# Compile and link Bluesim intermediate files into a Bluesim executable
+
+SIM_EXE_FILE = exe_HW_sim
+
+BSC_C_FLAGS += \
+	-Xc++  -D_GLIBCXX_USE_CXX11_ABI=0 \
+	-Xl -v \
+	-Xc -O1 -Xc++ -O1 \
+
+.PHONY: simulator
+simulator:
+	@echo "INFO: linking bsc-compiled objects into Bluesim executable"
+	bsc -sim -parallel-sim-link 8 +RTS -K32M -RTS \
+		$(TMP_DIRS) \
+		-e $(TOPMODULE) -o ./$(SIM_EXE_FILE) \
+		$(BSC_C_FLAGS) \
+		$(REPO)/src_Testbench/Top/C_Imported_Functions.c
+	@echo "INFO: linked bsc-compiled objects into Bluesim executable"
+
+# ================================================================

src_Core/RISCY_OOO/fpgautils/lib/ResetGuard.bsv

@@ -27,6 +27,18 @@ interface ResetGuard;
     method Bool isReady;
 endinterface
 
+`ifdef BSIM
+module mkResetGuard(ResetGuard);
+    Reg#(Bool) ready <- mkReg(False);
+
+    (* no_implicit_conditions, fire_when_enabled *)
+    rule rl_ready;
+        ready <= True;
+    endrule
+
+    method isReady = ready;
+endmodule
+`else
 import "BVI" reset_guard =
 module mkResetGuard(ResetGuard);
     default_clock clk(CLK);
@@ -36,3 +48,4 @@ module mkResetGuard(ResetGuard);
 
     schedule (isReady) CF (isReady);
 endmodule
+`endif

src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv

@@ -76,10 +76,15 @@ module mkIntDivUnsignedSim(IntDivUnsignedImport);
         let {dividend, user} = dividendQ.first;
         let divisor = divisorQ.first;
 
+        // Be careful to avoid divide-by-zero in bluesim's C++, which turns
+        //   res = cond ? exp1 : exp2
+        // into
+        //   tmp1 = exp1; tmp2 = exp2; res = cond ? tmp1 : tmp2
+        // so we must give a fake non-zero input even if it looks unused.
         UInt#(64) a = unpack(dividend);
-        UInt#(64) b = unpack(divisor);
-        Bit#(64) q = pack(a / b);
-        Bit#(64) r = pack(a % b);
+        UInt#(64) b = divisor == 0 ? 1 : unpack(divisor);
+        Bit#(64) q = divisor == 0 ? maxBound : pack(a / b);
+        Bit#(64) r = divisor == 0 ? dividend : pack(a % b);
         respQ.enq(tuple2({q, r}, user));
     endrule