Allow read/write of dpc

2020-06-17 11:42:58 +01:00
parent 4f4bbbbdcb
commit 0e7df46dce
1 changed files with 4 additions and 1 deletions
--- a/src_Core/CPU/CsrFile.bsv
+++ b/src_Core/CPU/CsrFile.bsv
@@ -799,7 +799,10 @@ module mkCsrFile #(Data hartid)(CsrFile);

 `ifdef INCLUDE_GDB_CONTROL
           CSRdcsr:       rg_dcsr;    // TODO: take NMI into account (cf. Piccolo/Flute)
-           // CSRdpc:        rg_dpc; // TODO: currently invisible to software due to it being a cap register
+           CSRdpc:        interface Reg;
+                              method _write (x) = action rg_dpc <= setAddrUnsafe(rg_dpc, x); endaction;
+                              method _read = getAddr(rg_dpc);
+                          endinterface
           CSRdscratch0:  rg_dscratch0;
           CSRdscratch1:  rg_dscratch1;
 `endif