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l1 tlb performance metrics working

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This commit is contained in:
Akilan Selvacoumar
2026-04-09 13:31:59 +01:00
parent af459956b7
commit 0e8b7f38dc
4 changed files with 3706 additions and 285461 deletions
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3699
0001-enabled-performance-counters.patch Normal file
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Tests/isa/testC
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285461
builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt
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7
src_Core/RISCY_OOO/procs/lib/DTlb.bsv
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@@ -242,6 +242,7 @@ module mkDTlb#(
rule incrAllMissCycles(doStats);
function Bool isMiss(DTlbWait x) = x != None;
when(all(isMiss, readVReg(pendWait)), allMissCycles.incr(1));
$display("L1TlballMissCycles = %0d", allMissCycles);
endrule
// `endif
// `ifdef PERFORMANCE_MONITORING
@@ -361,11 +362,15 @@ module mkDTlb#(
if(doStats) begin
if(isValid(respForOtherReq)) begin
missPeerLat.incr(zeroExtend(lat));
$display("L1 TLB miss");
$display("L1TLBmissPeerLat = %0d", missPeerLat);
missPeerCnt.incr(1);
end
else begin
missParentLat.incr(zeroExtend(lat));
missParentCnt.incr(1);
$display("L1 TLB parent miss");
$display("L1TLBmissParentCnt = %0d", missParentCnt);
end
end
// `endif
@@ -512,6 +517,7 @@ module mkDTlb#(
// perf: hit under miss
if(doStats && readVReg(pendWait) != replicate(None)) begin
hitUnderMissCnt.incr(1);
$display("L1TlbhitUnderMissCnt = %0d", hitUnderMissCnt);
end
// `endif
end
@@ -568,6 +574,7 @@ module mkDTlb#(
// `ifdef PERF_COUNT
// perf: access
if(doStats) begin
$display("L1 TLB inc");
accessCnt.incr(1);
end
// `endif