Fix Bluesim build (synced from Verilator Makefile)
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@@ -10,8 +10,10 @@ RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)
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CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv
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CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib
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# ALL_RISCY_DIRS = $(RISCY_DIRS)
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ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS)
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ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS)
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# ================================================================
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@@ -26,13 +28,16 @@ BSC_COMPILATION_FLAGS += \
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-D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \
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-D SV39 \
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-D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \
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-D CheriBusBytes=8 \
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-D CheriMasterIDWidth=1 \
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-D CheriTransactionIDWidth=5 \
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-D SHIFT_BARREL \
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-D MULT_SYNTH \
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-D Near_Mem_Caches \
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-D FABRIC64 \
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-D CheriBusBytes=8 \
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-D CheriMasterIDWidth=1 \
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-D CheriTransactionIDWidth=5 \
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-D CAP128 -D BLUESIM \
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-D MEM64 \
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-D RISCV \
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# Default ISA test
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34
builds/RV64ACDFIMSU_Toooba_bluesim/TagTableStructure.bsv
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34
builds/RV64ACDFIMSU_Toooba_bluesim/TagTableStructure.bsv
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@@ -0,0 +1,34 @@
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/*-
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* @BERI_LICENSE_HEADER_START@
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*
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* Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
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* license agreements. See the NOTICE file distributed with this work for
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* additional information regarding copyright ownership. BERI licenses this
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* file to you under the BERI Hardware-Software License, Version 1.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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*
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* http://www.beri-open-systems.org/legal/license-1-0.txt
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*
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* Unless required by applicable law or agreed to in writing, Work distributed
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* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* @BERI_LICENSE_HEADER_END@
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*/
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// This file was generated by the tagsparams.py script
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// 2020-03-24 15:49:40.494187
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import Vector::*;
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Vector#(2, Integer) tableStructure = cons(0, cons(64, nil));
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Integer table_end_addr = 'hbffff000;
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Integer table_start_addr = 'hbf7df080;
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Integer covered_start_addr = 'h80000000;
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Integer covered_mem_size = 'h3fffc000;
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