Fix Bluesim build (synced from Verilator Makefile)

This commit is contained in:
Jessica Clarke
2020-07-05 21:28:19 +01:00
parent 027b769904
commit 106f70e42b
2 changed files with 43 additions and 4 deletions

View File

@@ -10,8 +10,10 @@ RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)
CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv
CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib
# ALL_RISCY_DIRS = $(RISCY_DIRS)
ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS)
ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS)
# ================================================================
@@ -26,13 +28,16 @@ BSC_COMPILATION_FLAGS += \
-D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \
-D SV39 \
-D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \
-D CheriBusBytes=8 \
-D CheriMasterIDWidth=1 \
-D CheriTransactionIDWidth=5 \
-D SHIFT_BARREL \
-D MULT_SYNTH \
-D Near_Mem_Caches \
-D FABRIC64 \
-D CheriBusBytes=8 \
-D CheriMasterIDWidth=1 \
-D CheriTransactionIDWidth=5 \
-D CAP128 -D BLUESIM \
-D MEM64 \
-D RISCV \
# Default ISA test

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@@ -0,0 +1,34 @@
/*-
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* @BERI_LICENSE_HEADER_START@
*
* Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. BERI licenses this
* file to you under the BERI Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.beri-open-systems.org/legal/license-1-0.txt
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @BERI_LICENSE_HEADER_END@
*/
// This file was generated by the tagsparams.py script
// 2020-03-24 15:49:40.494187
import Vector::*;
Vector#(2, Integer) tableStructure = cons(0, cons(64, nil));
Integer table_end_addr = 'hbffff000;
Integer table_start_addr = 'hbf7df080;
Integer covered_start_addr = 'h80000000;
Integer covered_mem_size = 'h3fffc000;