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Move to config registers here as this affects scheduling.

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jon
2021-04-07 17:47:49 +01:00
parent 3f059cbd94
commit 12ac14c1ca
1 changed files with 11 additions and 10 deletions
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21
src_Core/RISCY_OOO/procs/lib/SplitLSQ.bsv
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@@ -42,6 +42,7 @@ import CCTypes::*;
import Vector::*;
import GetPut::*;
import Assert::*;
import ConfigReg::*;
import Ehr::*;
import Map::*;
import HasSpecBits::*;
@@ -633,16 +634,16 @@ module mkSplitLSQ(SplitLSQ);
// entry valid bits
Vector#(LdQSize, Ehr#(2, Bool)) ld_valid <- replicateM(mkEhr(False));
// entry contents
Vector#(LdQSize, Reg#(InstTag)) ld_instTag <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(LdQMemFunc)) ld_memFunc <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(Bool)) ld_unsigned <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(MemDataByteEn)) ld_byteEn <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(Bool)) ld_allowCap <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(Bool)) ld_acq <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(Bool)) ld_rel <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(Maybe#(PhyDst))) ld_dst <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(Bit#(16))) ld_pc_hash <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(Bool)) ld_waitForOlderSt <- replicateM(mkRegU);
Vector#(LdQSize, Reg#(InstTag)) ld_instTag <- replicateM(mkConfigRegU);
Vector#(LdQSize, Reg#(LdQMemFunc)) ld_memFunc <- replicateM(mkConfigRegU);
Vector#(LdQSize, Reg#(Bool)) ld_unsigned <- replicateM(mkConfigRegU);
Vector#(LdQSize, Reg#(MemDataByteEn)) ld_byteEn <- replicateM(mkConfigRegU);
Vector#(LdQSize, Reg#(Bool)) ld_allowCap <- replicateM(mkConfigRegU);
Vector#(LdQSize, Reg#(Bool)) ld_acq <- replicateM(mkConfigRegU);
Vector#(LdQSize, Reg#(Bool)) ld_rel <- replicateM(mkConfigRegU);
Vector#(LdQSize, Reg#(Maybe#(PhyDst))) ld_dst <- replicateM(mkConfigRegU);
Vector#(LdQSize, Reg#(Bit#(16))) ld_pc_hash <- replicateM(mkConfigRegU);
Vector#(LdQSize, Reg#(Bool)) ld_waitForOlderSt <- replicateM(mkConfigRegU);
Vector#(LdQSize, Ehr#(2, Addr)) ld_paddr <- replicateM(mkEhr(?));
Vector#(LdQSize, Ehr#(2, Bool)) ld_isMMIO <- replicateM(mkEhr(?));
Vector#(LdQSize, Ehr#(2, MemDataByteEn)) ld_shiftedBE <- replicateM(mkEhr(?));