Merge branch 'parallel-build' into CHERI

2020-04-27 15:19:05 +01:00
parent 5693af05e5 dfde021eb6
commit 13d020cb9e
6 changed files with 180 additions and 40 deletions
--- a/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile
+++ b/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile
@@ -25,20 +25,21 @@ ARCH ?= RV64ACDFIMSU
 # ================================================================
 # RISC-V config macros passed into Bluespec 'bsc' compiler

-BSC_COMPILATION_FLAGS += \
-	-D RISCV \
-	-D RV64 \
-	-D ISA_PRIV_M  -D ISA_PRIV_U  -D ISA_PRIV_S  \
-	-D SV39  \
-	-D ISA_I  -D ISA_M  -D ISA_A  -D ISA_F  -D ISA_D  -D ISA_FD_DIV  -D ISA_C  \
-	-D SHIFT_BARREL    \
-	-D MULT_SYNTH    \
-	-D Near_Mem_Caches    \
-	-D FABRIC64    \
-	-D CAP128 \
-	-D MEM64 \
-	-D RVFI_DII     \
-	-D RVFI
+MORE_DEFINES = RV64 \
+               ISA_PRIV_M ISA_PRIV_U ISA_PRIV_S \
+               SV39 \
+               ISA_I ISA_M ISA_A ISA_F ISA_D ISA_FD_DIV ISA_C \
+               SHIFT_BARREL \
+               MULT_SYNTH \
+               Near_Mem_Caches \
+               FABRIC64 \
+               CAP128 \
+               MEM64 \
+               RVFI_DII \
+               RVFI \
+               RISCV
+BSC_DEFINES += $(MORE_DEFINES)
+BSC_COMPILATION_FLAGS += $(addprefix -D , $(MORE_DEFINES))

 # Default ISA test

--- a/builds/RV64ACDFIMSU_Toooba_verilator/Makefile
+++ b/builds/RV64ACDFIMSU_Toooba_verilator/Makefile
@@ -23,18 +23,19 @@ ARCH ?= RV64ACDFIMSU
 # ================================================================
 # RISC-V config macros passed into Bluespec 'bsc' compiler

-BSC_COMPILATION_FLAGS += \
-	-D RV64 \
-	-D ISA_PRIV_M  -D ISA_PRIV_U  -D ISA_PRIV_S  \
-	-D SV39  \
-	-D ISA_I  -D ISA_M  -D ISA_A  -D ISA_F  -D ISA_D  -D ISA_FD_DIV  -D ISA_C  \
-	-D SHIFT_BARREL    \
-	-D MULT_SYNTH    \
-	-D Near_Mem_Caches    \
-	-D FABRIC64    \
-	-D CAP128 \
-	-D MEM64 \
-	-D RISCV \
+MORE_DEFINES = RV64 \
+               ISA_PRIV_M ISA_PRIV_U ISA_PRIV_S \
+               SV39 \
+               ISA_I ISA_M ISA_A ISA_F ISA_D ISA_FD_DIV ISA_C \
+               SHIFT_BARREL \
+               MULT_SYNTH \
+               Near_Mem_Caches \
+               FABRIC64 \
+               CAP128 \
+               MEM64 \
+               RISCV
+BSC_DEFINES += $(MORE_DEFINES)
+BSC_COMPILATION_FLAGS += $(addprefix -D , $(MORE_DEFINES))


 # Default ISA test
--- a/builds/Resources/Include_Common.mk
+++ b/builds/Resources/Include_Common.mk
@@ -55,7 +55,7 @@ TOPMODULE ?= mkTop_HW_Side

 BSC_COMPILATION_FLAGS += \
 	-keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \
-	-suppress-warnings G0020    \
+	-suppress-warnings G0020 -steps-max-intervals 10000000   \
 	+RTS -K128M -RTS  -show-range-conflict

 # ================================================================
@@ -63,6 +63,7 @@ BSC_COMPILATION_FLAGS += \

 EXAMPLE ?= PLEASE_DEFINE_EXAMPLE_PATH_TO_ELF

+
 .PHONY: run_example
 run_example:
 	make -C  $(TESTS_DIR)/elf_to_hex
@@ -95,7 +96,7 @@ isa_tests:

 .PHONY: clean
 clean:
-	rm -r -f  *~  Makefile_*  symbol_table.txt  build_dir  obj_dir
+	rm -r -f  *~  Makefile_*  symbol_table.txt  build_dir/*  obj_dir Verilog_RTL/*

 .PHONY: full_clean
 full_clean: clean
--- a/builds/Resources/Include_RISCY_Config.mk
+++ b/builds/Resources/Include_RISCY_Config.mk
@@ -69,13 +69,15 @@ XILINX_FP_FMA_LATENCY = 3
 XILINX_INT_MUL_LATENCY = 2


-BSC_COMPILATION_FLAGS += \
-	-D CORE_$(CORE_SIZE) \
-	-D NUM_CORES=$(CORE_NUM) \
-	-D CACHE_$(CACHE_SIZE) \
-        -D XILINX_FP_FMA_LATENCY=$(XILINX_FP_FMA_LATENCY) \
-        -D XILINX_INT_MUL_LATENCY=$(XILINX_INT_MUL_LATENCY) \
-	-D USE_BSV_BRAM_SYNC_FIFO \
+NEW_DEFINES = \
+	CORE_$(CORE_SIZE) \
+	NUM_CORES=$(CORE_NUM) \
+	CACHE_$(CACHE_SIZE) \
+        XILINX_FP_FMA_LATENCY=$(XILINX_FP_FMA_LATENCY) \
+        XILINX_INT_MUL_LATENCY=$(XILINX_INT_MUL_LATENCY) \
+	USE_BSV_BRAM_SYNC_FIFO
+BSC_DEFINES += $(NEW_DEFINES)
+BSC_COMPILATION_FLAGS += $(addprefix -D , $(NEW_DEFINES))


 # TODO:
--- a/builds/Resources/Include_verilator.mk
+++ b/builds/Resources/Include_verilator.mk
@@ -9,17 +9,34 @@

 RTL_GEN_DIRS = -vdir Verilog_RTL  -bdir build_dir  -info-dir build_dir

+.depends.mk: $(REPO)/builds/Resources/genDependencies.tcl build_dir
+	$(info WHAAAAAAAT $(BSC_DEFINES))
+	BSC_PATH=$(BSC_PATH) \
+	BSC_DEFINES="$(BSC_DEFINES)" \
+	BSC_BUILDDIR=build_dir \
+	BSC_TOPFILE=$(REPO)/src_Testbench/Top/Top_HW_Side.bsv \
+	OUTPUTFILE=$@ \
+	$<
+
 build_dir:
 	mkdir -p $@

 Verilog_RTL:
 	mkdir -p $@

+include .depends.mk
+
+%.bo:
+	$(info building $@)
+	bsc -verilog -elab -bdir build_dir -vdir Verilog_RTL $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
+
 .PHONY: compile
-compile:  build_dir  Verilog_RTL
-	@echo  "INFO: Verilog RTL generation ..."
-	bsc -u -elab -verilog  $(RTL_GEN_DIRS)  $(BSC_COMPILATION_FLAGS)  -p $(BSC_PATH)  $(TOPFILE)
-	@echo  "INFO: Verilog RTL generation finished"
+compile: .depends.mk build_dir Verilog_RTL build_dir/Top_HW_Side.bo
+#Verilog_RTL/mkTop_HW_Side.v:  build_dir Verilog_RTL /tmp/src_dir $(VERILOG_SUB_MODULES)
+#Verilog_RTL/mkTop_HW_Side.v: $(TOPFILE) build_dir/Top_HW_Side.bo build_dir Verilog_RTL
+#	@echo  "INFO: Verilog RTL generation ..."
+#	bsc -u -verilog  $(RTL_GEN_DIRS)  $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
+#	@echo  "INFO: Verilog RTL generation finished"

 # ================================================================
 # Compile and link Verilog RTL sources into an verilator executable
@@ -45,7 +62,7 @@ VTOP                = V$(TOPMODULE)_edited
 VERILATOR_RESOURCES = $(REPO)/builds/Resources/Verilator_resources

 .PHONY: simulator
-simulator:
+simulator: build_dir/Top_HW_Side.bo
 	@echo "INFO: Verilating Verilog files (in newly created obj_dir)"
 	sed  -f $(VERILATOR_RESOURCES)/sed_script.txt  Verilog_RTL/$(TOPMODULE).v > tmp1.v
 	cat  $(VERILATOR_RESOURCES)/verilator_config.vlt \
--- a/builds/Resources/genDependencies.tcl
+++ b/builds/Resources/genDependencies.tcl
@@ -0,0 +1,118 @@
+#! /usr/bin/env bluetcl
+#
+# Copyright (c) 2020 Alexandre Joannou
+# All rights reserved.
+#
+# This software was developed by SRI International and the University of
+# Cambridge Computer Laboratory (Department of Computer Science and
+# Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
+# DARPA SSITH research programme.
+#
+# @BERI_LICENSE_HEADER_START@
+#
+# Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  BERI licenses this
+# file to you under the BERI Hardware-Software License, Version 1.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at:
+#
+#   http://www.beri-open-systems.org/legal/license-1-0.txt
+#
+# Unless required by applicable law or agreed to in writing, Work distributed
+# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations under the License.
+#
+# @BERI_LICENSE_HEADER_END@
+#
+
+namespace import ::Bluetcl::*
+
+# there does not seam to be a nice "getopt" in tcl, so for now, falling back on:
+#
+# - env variables:
+# BSC_PATH
+# BSC_DEFINES
+# BSC_BUILDDIR
+# BSC_TOPFILE
+# OUTPUTFILE
+#
+# - if argv is non empty, each arg is passed individually to a flags set command
+#   (that is, can't pass flags that expect arguments themselves like -D XXX)
+################################################################################
+
+if { [info exists env(BSC_PATH)] } {
+  set path $env(BSC_PATH)
+} else {
+  #set path ".:+"
+  set path "../../libs/BlueStuff:../../libs/BlueStuff/AXI:../../libs/BlueStuff/BlueUtils:../../libs/BlueStuff/BlueBasics:../../src_Core/RISCY_OOO/procs/RV64G_OOO:../../src_Core/RISCY_OOO/procs/lib:../../src_Core/RISCY_OOO/coherence/src:../../src_Core/RISCY_OOO/fpgautils/lib:../../src_Core/RISCY_OOO/connectal/bsv:../../src_Core/RISCY_OOO/connectal/tests/spi:../../src_Core/RISCY_OOO/connectal/lib/bsv:../../src_Core/RISCY_OOO/../../src_Verifier:../../src_Core/RISCY_OOO/../../src_Verifier/BSV-RVFI-DII:../../src_Core/RISCY_OOO/../CHERI:../../src_Core/RISCY_OOO/../../libs/cheri-cap-lib:../../src_Core/CPU:../../src_Core/ISA:../../src_Core/Core:../../src_Core/PLIC:../../src_Core/Debug_Module:../../src_Core/BSV_Additional_Libs:../../src_Testbench/Top:../../src_Testbench/SoC:../../libs/TagController/TagController:../../libs/TagController/TagController/CacheCore:+"
+}
+
+if { [info exists env(BSC_DEFINES)] } {
+  set defines [split $env(BSC_DEFINES)]
+} else {
+  #set defines {}
+  set defines [split "RISCV RV64 ISA_PRIV_M ISA_PRIV_U ISA_PRIV_S SV39 ISA_I ISA_M ISA_A ISA_F ISA_D ISA_FD_DIV ISA_C SHIFT_BARREL MULT_SYNTH Near_Mem_Caches FABRIC64 CAP128 MEM64 BSIM CORE_SMALL NUM_CORES=1 CACHE_SMALL XILINX_FP_FMA_LATENCY=3 XILINX_INT_MUL_LATENCY=2 USE_BSV_BRAM_SYNC_FIFO"]
+}
+
+if { [info exists env(BSC_BUILDDIR)] } {
+  set builddir $env(BSC_BUILDDIR)
+} else {
+  set builddir "build"
+}
+
+if { [info exists env(BSC_TOPFILE)] } {
+  set topfile $env(BSC_TOPFILE)
+} else {
+  set topfile "Top.bsv"
+}
+
+if { [info exists env(OUTPUTFILE)] } {
+  set outputfile $env(OUTPUTFILE)
+} else {
+  set outputfile ".depends.mk"
+}
+
+# debug prints
+#puts "path: $path"
+#puts "defines: $defines"
+#puts "builddir: $builddir"
+#puts "topfile: $topfile"
+#puts "outputfile: $outputfile"
+#puts "argv: $argv"
+
+# setting compiler flags
+################################################################################
+
+flags set -p $path
+flags set -bdir $builddir
+flags set -verilog
+foreach i $defines {
+  flags set -D $i
+}
+if { $argc > 0 } { foreach i $argv { flags set $i } }
+
+# output of "depend make" seams to be of the form
+# { {tgtA {depA0 depA1 ...}}
+#   {tgtB {depB0 depB1 ...}}
+#   ...
+# }
+# reformating it for make
+################################################################################
+try {
+  set res [depend make $topfile]
+} finally {
+  if { [info exists res] } {
+    set fd [open $outputfile w]
+    foreach i $res {
+      set tgt [lindex $i 0]
+      set deps [join [lindex $i 1]]
+      puts $fd [append tgt ": " $deps]
+    }
+    close $fd
+    puts "generated make dependency rules for \"$topfile\" in: $outputfile"
+  } else {
+    puts "could not generate make dependency rules for \"$topfile\""
+  }
+}