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Prefetcher code cleanup

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This commit is contained in:
Karlis Susters
2023-05-10 23:55:05 +01:00
parent 05e5ad5076
commit 1776ba3317
1 changed files with 5 additions and 6 deletions
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11
src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
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@@ -1213,17 +1213,16 @@ typedef struct {
module mkBRAMStridePCPrefetcher(PCPrefetcher)
provisos(
NumAlias#(strideTableSize, 512),
NumAlias#(cLinesAheadToPrefetch, 2), // TODO fetch more if have repeatedly hit an entry, and if stride big
NumAlias#(cLinesAheadToPrefetch, 2),
Alias#(strideTableIndexT, Bit#(TLog#(strideTableSize)))
);
//Vector#(strideTableSize, Reg#(StrideEntry)) strideTable <- replicateM(mkReg(unpack(0)));
RWBramCore#(strideTableIndexT, StrideEntry) strideTable <- mkRWBramCoreForwarded;
FIFOF#(Tuple3#(Addr, Bit#(16), HitOrMiss)) memAccesses <- mkSizedBypassFIFOF(8);
Reg#(Tuple3#(Addr, Bit#(16), HitOrMiss)) rdRespEntry <- mkReg(?);
Fifo#(8, Addr) addrToPrefetch <- mkOverflowPipelineFifo;
FIFO#(Tuple3#(StrideEntry, Addr, Bit#(16))) strideEntryForPrefetch <- mkBypassFIFO();
Reg#(Maybe#(Bit#(4))) cLinesPrefetchedLatest <- mkReg(?);
Reg#(Maybe#(Bit#(4))) cLinesPrefetchedLatest <- mkReg(Invalid);
PulseWire holdReadReq <- mkPulseWire;
rule sendReadReq if (!holdReadReq);
@@ -1950,9 +1949,9 @@ module mkLLDPrefetcher(Prefetcher);
`ifdef DATA_PREFETCHER_BLOCK
let m <- mkBlockPrefetcher;
`elsif DATA_PREFETCHER_STRIDE
doAssert(False, "Illegal data prefetcher type for LL cache!")
`elsif DATA_PREFETCHER_STRIDE
doAssert(False, "Illegal data prefetcher type for LL cache!")
doAssert(False, "Illegal data prefetcher type for LL cache!");
`elsif DATA_PREFETCHER_STRIDE_ADAPTIVE
doAssert(False, "Illegal data prefetcher type for LL cache!");
`elsif DATA_PREFETCHER_MARKOV
let m <- mkBRAMMarkovPrefetcher;
`elsif DATA_PREFETCHER_MARKOV_ON_HIT