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Use DRegOR instead of immitating latching behaviour.

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This commit is contained in:
jon
2020-12-15 16:18:36 +00:00
parent d64df09d82
commit 17a7a32092
4 changed files with 18 additions and 34 deletions
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10
src_Core/RISCY_OOO/coherence/src/IBank.bsv
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@@ -59,7 +59,7 @@ import LatencyTimer::*;
import RandomReplace::*;
`ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import SpecialWires::*;
import BlueUtils::*;
`endif
export ICRqStuck(..);
@@ -193,11 +193,7 @@ module mkIBank#(
Count#(Data) ldMissLat <- mkCount(0);
`endif
`ifdef PERFORMANCE_MONITORING
Array #(Wire #(EventsCache)) perf_events <- mkDWireOR (2, unpack (0));
Reg #(EventsCache) perf_events_reg <- mkConfigReg(unpack(0));
rule update_events_reg;
perf_events_reg <= perf_events[0];
endrule
Array #(Reg #(EventsCache)) perf_events <- mkDRegOR (2, unpack (0));
`endif
function Action incrReqCnt;
action
@@ -846,7 +842,7 @@ module mkIBank#(
endcase);
endmethod
`ifdef PERFORMANCE_MONITORING
method EventsCache events = perf_events_reg;
method EventsCache events = perf_events[0];
`endif
endmodule

10
src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
View File

@@ -62,7 +62,7 @@ import LatencyTimer::*;
import RandomReplace::*;
`ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import SpecialWires::*;
import BlueUtils::*;
`endif
export L1CRqStuck(..);
@@ -212,11 +212,7 @@ module mkL1Bank#(
Count#(Data) amoMissLat <- mkCount(0);
`endif
`ifdef PERFORMANCE_MONITORING
Array #(Wire #(EventsCache)) perf_events <- mkDWireOR (2, unpack (0));
Reg #(EventsCache) perf_events_reg <- mkConfigReg(unpack(0));
rule update_events_reg;
perf_events_reg <= perf_events[0];
endrule
Array #(Reg #(EventsCache)) perf_events <- mkDRegOR (2, unpack (0));
`endif
function Action incrReqCnt(MemOp op);
action
@@ -1130,7 +1126,7 @@ endfunction
endcase);
endmethod
`ifdef PERFORMANCE_MONITORING
method EventsCache events = perf_events_reg;
method EventsCache events = perf_events[0];
`endif
endmodule