Cheri-research/Toooba
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CSome style cleanups from chat with Alexandre.

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This commit is contained in:
jon
2020-12-11 16:44:59 +00:00
parent 1bae03da9c
commit 19a07882ab
3 changed files with 11 additions and 8 deletions
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6
src_Core/CPU/Core.bsv
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@@ -241,6 +241,10 @@ instance BitVectorable #(EventsCore, SizeOf#(SupCnt), EventsCoreElements) provis
function Vector#(EventsCoreElements, SupCnt) to_vector(EventsCore e) =
reverse(unpack(pack(e)));
endinstance
instance BitVectorable #(EventsCoreMem, SizeOf#(HpmRpt), EventsCoreMemElements) provisos (Bits #(EventsCoreMem, m));
function Vector#(EventsCoreMemElements, HpmRpt) to_vector(EventsCoreMem e) =
reverse(unpack(pack(e)));
endinstance
`endif
(* synthesize *)
@@ -1108,7 +1112,7 @@ module mkCore#(CoreId coreId)(Core);
endrule
Vector #(1, Bit #(Report_Width)) null_evt = replicate (0);
Vector #(31, Bit #(Report_Width)) mem_core_evts_vec = reverse(unpack({pack(coreFix.memExeIfc.events),0}));
Vector #(31, Bit #(Report_Width)) mem_core_evts_vec = to_large_vector (coreFix.memExeIfc.events);
Vector #(31, Bit #(Report_Width)) other_core_evts_vec = to_large_vector (hpm_core_events_reg);
Vector #(31, Bit #(Report_Width)) core_evts_vec = unpack(pack(mem_core_evts_vec) | pack(other_core_evts_vec));
Vector #(16, Bit #(Report_Width)) imem_evts_vec = replicate (0);//to_large_vector (near_mem.imem.events);

11
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -351,8 +351,8 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
`endif
`ifdef PERFORMANCE_MONITORING
EventsCoreMem events = unpack(0);
events.evt_LOAD_WAIT = truncate(lat);
events.evt_MEM_CAP_LOAD_TAG_SET = (d.tag) ? 1:0;
events.evt_LOAD_WAIT = saturating_truncate(lat);
events.evt_MEM_CAP_LOAD_TAG_SET = (d.tag) ? 1 : 0;
events_wire[1] <= events;
`endif
endmethod
@@ -380,8 +380,8 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
`ifdef PERFORMANCE_MONITORING
EventsCoreMem events = unpack(0);
if (waitSt.shiftedBE == -1) events.evt_MEM_CAP_STORE = 1;
events.evt_STORE_WAIT = truncate(lat);
events.evt_MEM_CAP_STORE_TAG_SET = (waitSt.shiftedData.tag) ? 1:0;
events.evt_STORE_WAIT = saturating_truncate(lat);
events.evt_MEM_CAP_STORE_TAG_SET = (waitSt.shiftedData.tag) ? 1 : 0;
events_wire[2] <= events;
`endif
// now figure out the data to be written
@@ -407,8 +407,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
`ifdef PERFORMANCE_MONITORING
EventsCoreMem events = unpack(0);
if (pack(e.byteEn) == -1) events.evt_MEM_CAP_STORE = 1;
events.evt_STORE_WAIT = truncate(lat);
events.evt_MEM_CAP_STORE_TAG_SET = pack(zeroExtend(countOnes(pack(e.line.tag))));
events.evt_STORE_WAIT = saturating_truncate(lat);
events_wire[2] <= events;
`endif
return tuple2(unpack(pack(e.byteEn)), e.line); // return SB entry

2
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
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@@ -1063,7 +1063,7 @@ typedef struct {
SupCnt evt_FP;
SupCnt evt_SC_SUCCESS;
SupCnt evt_LOAD_WAIT;
SupCnt evt_STORE_WAIT; // XXX Don't think we can make this make sense for Toooba. Store delays overlap so we can't get a single number that tells us the cycles spent waiting for store delays. Toooba seems to measure the delay of each store independently. Maybe we could do this with ~8bits per element? One report per cycle?
SupCnt evt_STORE_WAIT;
SupCnt evt_FENCE;
SupCnt evt_F_BUSY_NO_CONSUME; // XXX
SupCnt evt_D_BUSY_NO_CONSUME; // XXX