Include both execute redirect and commit redirect in "redirect" counter.

src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv

@@ -75,6 +75,7 @@ import Types::*;
 `endif
 import IndexedMultiset::*;
 import Cur_Cycle :: *;
+import DReg :: *;
 
 // ================================================================
 // For fv_decode_C function and related types and definitions
@@ -154,6 +155,9 @@ interface FetchStage;
 
     // performance
     interface Perf#(DecStagePerfType) perf;
+`ifdef PERFORMANCE_MONITORING
+    method Bool redirect_evt;
+`endif
 endinterface
 
 // PC "compression" types to facilitate storing common upper PC bits in a
@@ -414,6 +418,9 @@ module mkFetchStage(FetchStage);
         });
     endrule
 `endif
+`ifdef PERFORMANCE_MONITORING
+    Reg#(Bool) redirect_evt <- mkDReg(False);
+`endif
 
     rule updatePcInBtb;
         nextAddrPred.put_pc(pc_reg[pc_final_port]);
@@ -897,6 +904,9 @@ module mkFetchStage(FetchStage);
         // this redirect may be caused by a trap/system inst in commit stage
         // we conservatively set wait for flush TODO make this an input parameter
         waitForFlush[2] <= True;
+`ifdef PERFORMANCE_MONITORING
+        redirect_evt <= True;
+`endif
     endmethod
 
 `ifdef INCLUDE_GDB_CONTROL
@@ -995,4 +1005,7 @@ module mkFetchStage(FetchStage);
 `endif
     endinterface
 
+`ifdef PERFORMANCE_MONITORING
+    method Bool redirect_evt = redirect_evt._read;
+`endif
 endmodule