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Merge remote-tracking branch 'karlis/CHERI' into ks980-prefetch

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Jonathan Woodruff
2023-04-25 15:42:25 +00:00
parent f56dcf6c0a 0554fad990
commit 21a45d6e0d
2 changed files with 3 additions and 3 deletions
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2
builds/Resources/Include_RISCY_Config.mk
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@@ -47,7 +47,7 @@ CHECK_DEADLOCK ?= true
RENAME_DEBUG ?= false
INSTR_PREFETCHER_LOCATION ?= L1
INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW_TARGET
DATA_PREFETCHER_LOCATION ?= NONE
DATA_PREFETCHER_LOCATION ?= L1
DATA_PREFETCHER_TYPE ?= MARKOV_ON_HIT_2
# clk frequency depends on core size

4
src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
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@@ -526,7 +526,7 @@ module mkTargetTableDouble(TargetTableDouble#(narrowTableSize, wideTableSize)) p
NumAlias#(wideTableIdxBits, TLog#(wideTableSize)),
NumAlias#(narrowTableTagBits, TSub#(24, narrowTableIdxBits)),
NumAlias#(wideTableTagBits, TSub#(24, wideTableIdxBits)),
NumAlias#(narrowDistanceBits, 10),
NumAlias#(narrowDistanceBits, 16),
NumAlias#(narrowMaxDistanceAbs, TExp#(TSub#(narrowDistanceBits, 1))),
Alias#(narrowTargetEntryT, NarrowTargetEntry#(narrowTableTagBits, narrowDistanceBits)),
Alias#(wideTargetEntryT, WideTargetEntry#(wideTableTagBits)),
@@ -1080,7 +1080,7 @@ module mkMarkovOnHit2Prefetcher(Prefetcher) provisos
);
Reg#(LineAddr) lastChildRequest <- mkReg(0);
Reg#(Vector#(numLastRequests, Bit#(32))) lastAddrRequests <- mkReg(replicate(0));
TargetTableDouble#(2048, 256) targetTable <- mkTargetTableDouble;
TargetTableDouble#(65536, 4096) targetTable <- mkTargetTableDouble;
Fifo#(8, LineAddr) highPriorityPrefetches <- mkOverflowBypassFifo;
Fifo#(8, LineAddr) lowPriorityPrefetches <- mkOverflowBypassFifo;