Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Propagate a CapPipe through the PC of each instruction record.

Browse Source
This commit is contained in:
Jonathan Woodruff
2020-03-23 17:24:05 +00:00
parent 2aa902f61a
commit 22938d2384
3 changed files with 14 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -152,7 +152,7 @@ endinterface
// we apply actions the end of commit rule
// use struct to record actions to be done
typedef struct {
Addr pc;
CapPipe pc;
Addr addr;
Trap trap;
Bit #(32) orig_inst;
@@ -212,7 +212,7 @@ function Maybe#(RVFI_DII_Execution#(DataSz,DataSz)) genRVFI(ToReorderBuffer rot,
rvfi_rs2_addr: rot.orig_inst[24:20],
rvfi_rs1_data: ?,
rvfi_rs2_data: ?,
rvfi_pc_rdata: rot.pc,
rvfi_pc_rdata: getAddr(rot.pc),
rvfi_pc_wdata: next_pc,
rvfi_mem_wdata: wdata,
rvfi_rd_addr: rd,
@@ -742,8 +742,8 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
if (! debugger_halt) begin
// trap handling & redirect
let trap_updates <- csrf.trap(trap.trap, trap.pc, trap.addr, trap.orig_inst);
let cap_trap_updates <- scaprf.trap(trap.trap, trap.pc, trap.addr, trap.orig_inst);
let trap_updates <- csrf.trap(trap.trap, getAddr(trap.pc), trap.addr, trap.orig_inst);
let cap_trap_updates <- scaprf.trap(trap.trap, getAddr(trap.pc), trap.addr, trap.orig_inst);
inIfc.redirectPc(trap_updates.new_pc
`ifdef RVFI_DII
, trap.x.diid + 1
@@ -787,7 +787,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
// kill everything, redirect, and increment epoch
inIfc.killAll;
inIfc.redirectPc(x.pc
inIfc.redirectPc(getAddr(x.pc)
`ifdef RVFI_DII
, x.diid
`endif
@@ -875,8 +875,8 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
end
// redirect (Sret and Mret redirect pc is got from CSRF)
Addr next_pc = x.ppc_vaddr_csrData matches tagged PPC .ppc ? getAddr(ppc) : (x.pc + 4);
doAssert(next_pc == x.pc + 4, "ppc must be pc + 4");
Addr next_pc = x.ppc_vaddr_csrData matches tagged PPC .ppc ? getAddr(ppc) : (getAddr(x.pc) + 4);
doAssert(next_pc == getAddr(x.pc) + 4, "ppc must be pc + 4");
`ifdef INCLUDE_TANDEM_VERIF
Maybe #(RET_Updates) m_ret_updates = no_ret_updates;
`endif
@@ -1052,7 +1052,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
else begin
if (verbose) $display("[doCommitNormalInst - %d] ", i, fshow(inst_tag), " ; ", fshow(x));
`ifdef RVFI
rvfis[i] = genRVFI(x, traceCnt + zeroExtend(whichTrace), getTSB(), x.pc + (is_16b_inst(x.orig_inst) ? 2:4));
rvfis[i] = genRVFI(x, traceCnt + zeroExtend(whichTrace), getTSB(), getAddr(x.pc) + (is_16b_inst(x.orig_inst) ? 2:4));
whichTrace = whichTrace + 1;
`endif

6
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
View File

@@ -352,7 +352,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
// This avoids doing incorrect work
incrEpochStallFetch;
// just place it in the reorder buffer
let y = ToReorderBuffer{pc: pc,
let y = ToReorderBuffer{pc: setAddr(cast(scaprf.rd(SCR_PCC)), pc).value,
orig_inst: orig_inst,
iType: dInst.iType,
dst: arch_regs.dst,
@@ -550,7 +550,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
end
RobInstState rob_inst_state = to_exec ? NotDone : Executed;
let y = ToReorderBuffer{pc: pc,
let y = ToReorderBuffer{pc: setAddr(cast(scaprf.rd(SCR_PCC)), pc).value,
orig_inst: orig_inst,
iType: dInst.iType,
dst: arch_regs.dst,
@@ -1091,7 +1091,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
end
RobInstState rob_inst_state = (to_exec || to_mem || to_FpuMulDiv) ? NotDone : Executed;
let y = ToReorderBuffer{pc: pc,
let y = ToReorderBuffer{pc: setAddr(cast(scaprf.rd(SCR_PCC)), pc).value,
orig_inst: orig_inst,
iType: dInst.iType,
dst: arch_regs.dst,

6
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
View File

@@ -59,7 +59,7 @@ typedef struct {
`endif
typedef struct {
Addr pc;
CapPipe pc;
Bit #(32) orig_inst; // original 16b or 32b instruction ([1:0] will distinguish 16b or 32b)
IType iType;
Maybe#(ArchRIndx) dst; // Invalid, GPR or FPR destination ("Rd")
@@ -219,7 +219,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
Integer sb_enq_port = 1; // write spec_bits
Integer sb_correctSpec_port = 2; // write spec_bits
Reg#(Addr) pc <- mkRegU;
Reg#(CapPipe) pc <- mkRegU;
Reg #(Bit #(32)) orig_inst <- mkRegU;
Reg#(IType) iType <- mkRegU;
Reg #(Maybe #(ArchRIndx)) rg_dst_reg <- mkRegU;
@@ -303,7 +303,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
endinterface);
end
method Addr getOrigPC = pc;
method Addr getOrigPC = getAddr(pc);
method Addr getOrigPredPC = predPcWire;
method Bit #(32) getOrig_Inst = orig_inst;