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Report writes to PCC as illegal instruction, not ASR violation

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This commit is contained in:
Peter Rugg
2020-07-23 15:40:28 +01:00
parent 97d89086a6
commit 27082ee2a9
3 changed files with 5 additions and 6 deletions
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1
src_Core/RISCY_OOO/procs/lib/CapChecks.bsvi
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@@ -19,7 +19,6 @@
`CAP_CHECK_FIELD(src1_type_not_reserved,"src1_type_not_reserved")
`CAP_CHECK_FIELD(src1_perm_subset_src2,"src1_perm_subset_src2")
`CAP_CHECK_FIELD(src1_derivable,"src1_derivable")
`CAP_CHECK_FIELD(scr_read_only,"scr_read_only")
`CAP_CHECK_FIELD(cfromptr_bypass,"cfromptr_bypass")
`CAP_CHECK_FIELD(ccseal_bypass,"ccseal_bypass")
`CAP_CHECK_FIELD(cap_exact,"cap_exact")

1
src_Core/RISCY_OOO/procs/lib/Decode.bsv
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@@ -969,7 +969,6 @@ function DecodeResult decode(Instruction inst, Bool cap_mode);
dInst.execFunc = tagged Alu Add;
regs.src1 = Invalid;
dInst.csr = tagged Invalid;
dInst.capChecks.scr_read_only = True;
end else begin
dInst.scr = Valid (scr);
end

9
src_Core/RISCY_OOO/procs/lib/Exec.bsv
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@@ -92,8 +92,6 @@ function Maybe#(CSR_XCapCause) capChecksExec(CapPipe a, CapPipe b, CapPipe ddc,
result = e2(SoftwarePermViolation);
else if (toCheck.src1_derivable && !isDerivable(a))
result = e1(LengthViolation);
else if (toCheck.scr_read_only && (toCheck.rn1 != 0))
result = Valid(CSR_XCapCause{cheri_exc_reg: {1,pack(SCR_PCC)}, cheri_exc_code: PermitASRViolation});
else if (toCheck.cap_exact && !cap_exact)
result = e1(RepresentViolation);
return result;
@@ -534,9 +532,12 @@ function Maybe#(Trap) checkForException(
else if(dInst.scr matches tagged Valid .scr) begin
Bool scr_has_priv = (prv >= pack(scr)[4:3]);
Bool unimplemented = (scr == SCR_None);
Bool writes_scr = regs.src1 == Valid (tagged Gpr 0) ? False : True;
Bool read_only = (scr == SCR_PCC);
Bool write_deny = (writes_scr && read_only);
Bool asr_deny = !getHardPerms(pcc).accessSysRegs && !(
scr == SCR_DDC);
if(!scr_has_priv || unimplemented) begin // Writes to PCC checked in capChecks
scr == SCR_DDC || scr == SCR_PCC);
if(!scr_has_priv || unimplemented || write_deny) begin
exception = Valid (Exception (IllegalInst));
end else if (asr_deny) begin
exception = Valid (CapException (CSR_XCapCause {cheri_exc_reg: {1'b1, pack(SCR_PCC)}, cheri_exc_code: PermitASRViolation}));