Cheri-research/Toooba
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Prepared repo for building on FPGA

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This commit is contained in:
Karlis Susters
2023-02-13 21:52:50 +00:00
parent 9d027a3f4b
commit 2c9428d1f3
4 changed files with 115 additions and 36 deletions
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25
builds/Resources/Include_RISCY_Config.mk
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@@ -45,6 +45,11 @@ SIM_LLC_ARBITER_LAT ?=
# default check cache deadlock and rename error
CHECK_DEADLOCK ?= true
RENAME_DEBUG ?= false
INSTR_PREFETCHER_LOCATION ?= L1
INSTR_PREFETCHER_TYPE ?= NEXT_LINE_ON_MISS
DATA_PREFETCHER_LOCATION ?= L1
DATA_PREFETCHER_TYPE ?= BLOCK
# clk frequency depends on core size
ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM))
@@ -62,6 +67,21 @@ $(error unsupported CACHE_SIZE)
endif
ifeq (,$(filter $(INSTR_PREFETCHER_LOCATION),NONE L1 L1LL LL))
$(error unsupported INSTR_PREFETCHER_LOCATION)
endif
ifeq (,$(filter $(INSTR_PREFETCHER_TYPE),NEXT_LINE_ON_MISS NEXT_LINE_ON_ALL SINGLE_WINDOW MULTI_WINDOW SINGLE_WINDOW_TARGET MULTI_WINDOW_TARGET))
$(error unsupported INSTR_PREFETCHER_TYPE)
endif
ifeq (,$(filter $(DATA_PREFETCHER_LOCATION),NONE L1 L1LL LL))
$(error unsupported DATA_PREFETCHER_LOCATION)
endif
ifeq (,$(filter $(DATA_PREFETCHER_TYPE),MARKOV BLOCK STRIDE))
$(error unsupported DATA_PREFETCHER_TYPE)
endif
# ================================================================
# These are taken from: RISCY_HOME/procs/scripts/Makefile.common
@@ -76,7 +96,10 @@ BSC_COMPILATION_FLAGS += \
-D XILINX_FP_FMA_LATENCY=$(XILINX_FP_FMA_LATENCY) \
-D XILINX_INT_MUL_LATENCY=$(XILINX_INT_MUL_LATENCY) \
-D USE_BSV_BRAM_SYNC_FIFO \
-D INSTR_PREFETCHER_IN_$(INSTR_PREFETCHER_LOCATION) \
-D INSTR_PREFETCHER_$(INSTR_PREFETCHER_TYPE) \
-D DATA_PREFETCHER_IN_$(DATA_PREFETCHER_LOCATION) \
-D DATA_PREFETCHER_$(DATA_PREFETCHER_TYPE)
# TODO:
# -D SELF_INV_CACHE -D L1D_MAX_HITS=$(SELF_INV_CACHE)