Merge pull request #14 from jrtc27/uncached-amo
MMIOPlatform.bsv: Discard write response for uncached AMOs
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@@ -282,6 +282,10 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
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// CRs, we record the AMO resp at processing time
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Reg#(Data) amoResp <- mkRegU;
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// For AMOs to the fabric, we end up with read and write responses, and need
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// to discard the latter. This tracks which of the two we're waiting for.
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Reg#(Bool) amoWaitWriteResp <- mkRegU;
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// we increment mtime periodically
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Reg#(Bit#(TLog#(CyclesPerTimeInc))) cycle <- mkReg(0);
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@@ -928,6 +932,7 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
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let req = MMIOCRq {addr:addr, func:tagged Ld, byteEn:?, data:?};
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mmio_fabric_adapter_core_side.request.put (req);
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state <= WaitResp;
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amoWaitWriteResp <= False;
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if (verbosity > 0) begin
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$display ("MMIOPlatform.rl_mmio_to_fabric_amo_req: addr 0x%0h", addr);
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@@ -941,7 +946,11 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
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&&& isAmo);
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MMIODataPRs dprs <- mmio_fabric_adapter_core_side.response.get;
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if (! dprs.valid) begin
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if (amoWaitWriteResp) begin
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// Discard the write response; we're now ready for another request
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state <= SelectReq;
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end
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else if (! dprs.valid) begin
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// Access fault
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let prs = tagged DataAccess dprs;
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cores[reqCore].pRs.enq (prs);
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@@ -958,7 +967,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
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let prs = tagged DataAccess (MMIODataPRs { valid: True, data: ld_val });
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cores[reqCore].pRs.enq (prs);
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state <= SelectReq;
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// Stay in WaitResp but wait to discard the write response
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amoWaitWriteResp <= True;
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if (verbosity > 1) begin
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$display ("MMIO_Platform.rl_mmio_from_fabric_amo_rsp: addr 0x%0h, size %0d, amofunc %0d",
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