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Config for L1D Stride-3 prefetcher

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This commit is contained in:
Karlis Susters
2023-03-07 12:33:51 +00:00
parent 76c0071c9e
commit 30a3aff5af
4 changed files with 132 additions and 4 deletions
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4
builds/Resources/Include_RISCY_Config.mk
View File

@@ -47,8 +47,8 @@ CHECK_DEADLOCK ?= true
RENAME_DEBUG ?= false
INSTR_PREFETCHER_LOCATION ?= NONE
INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW
DATA_PREFETCHER_LOCATION ?= L1LL
DATA_PREFETCHER_TYPE ?= BLOCK
DATA_PREFETCHER_LOCATION ?= L1
DATA_PREFETCHER_TYPE ?= STRIDE
# clk frequency depends on core size
ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM))

3
src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
View File

@@ -1,6 +1,7 @@
import ISA_Decls :: *;
import RWBramCore::*;
import FIFO::*;
import Fifos::*;
import FIFOF::*;
import SpecialFIFOs :: *;
import Ehr::*;
@@ -1193,7 +1194,7 @@ provisos(
FIFOF#(Tuple3#(Addr, Bit#(16), HitOrMiss)) memAccesses <- mkSizedBypassFIFOF(8);
Reg#(Tuple3#(Addr, Bit#(16), HitOrMiss)) rdRespEntry <- mkReg(?);
FIFO#(Addr) addrToPrefetch <- mkSizedFIFO(8);
Fifo#(8, Addr) addrToPrefetch <- mkOverflowPipelineFifo;
FIFO#(Tuple3#(StrideEntry, Addr, Bit#(16))) strideEntryForPrefetch <- mkBypassFIFO();
Reg#(Maybe#(Bit#(4))) cLinesPrefetchedLatest <- mkReg(?);
PulseWire holdReadReq <- mkPulseWire;

79
src_Core/RISCY_OOO/coherence/src/test/Prefetcher_test.bsv
View File

@@ -1,7 +1,7 @@
import Prefetcher::*;
import StmtFSM::*;
import Types::*;
import Fifos::*;
module mkTargetTableTest(Empty);
TargetTable#(64, 16) t <- mkTargetTable;
mkAutoFSM(
@@ -827,4 +827,81 @@ module mkMarkovPrefetcherTest(Empty);
endaction
endseq
);
endmodule
module mkOverflowPipelineFifoTest(Empty);
//let p <- mkMultipleWindowPrefetcher;
Fifo#(4, Bit#(8)) p <- mkOverflowPipelineFifo;
mkAutoFSM(
seq
// ----- Send misses and stuff to one window -----
action
p.enq('h01);
endaction
action
p.enq('h02);
endaction
action
p.enq('h03);
endaction
action
p.enq('h04);
endaction
action
let x = p.first;
p.deq;
doAssert(x == 'h01, "test fail!");
endaction
action
p.enq('h05);
let x = p.first;
p.deq;
doAssert(x == 'h02, "test fail!");
endaction
action
p.enq('h06);
endaction
action
p.enq('h07);
let x = p.first;
p.deq;
doAssert(x == 'h03, "test fail!");
endaction
action
p.enq('h08);
endaction
action
p.enq('h09);
let x = p.first;
p.deq;
doAssert(x == 'h05, "test fail!");
endaction
action
let x = p.first;
p.deq;
doAssert(x == 'h06, "test fail!");
endaction
action
let x = p.first;
p.deq;
doAssert(x == 'h07, "test fail!");
endaction
action
let x = p.first;
p.deq;
doAssert(x == 'h08, "test fail!");
endaction
action
let x = p.first;
p.deq;
doAssert(x == 'h09, "test fail!");
endaction
action
doAssert(!p.notEmpty, "test fail!");
endaction
action
$display("test done!");
endaction
endseq
);
endmodule

50
src_Core/RISCY_OOO/procs/lib/Fifos.bsv
View File

@@ -691,3 +691,53 @@ module mkCFSCountFifo#(function Bool isFound(t v, st k))(SCountFifo#(n, t, st))
deqEn[1] <= False;
endmethod
endmodule
module mkOverflowPipelineFifo( Fifo#(n, t) ) provisos (Bits#(t,tSz));
// A pipeline fifo that also allows enquing to it when full,
// discarding the oldest element
// n is size of fifo
// t is data type of fifo
Vector#(n, Reg#(t)) data <- replicateM(mkReg(unpack(0)));
Ehr#(2, Bit#(TLog#(n))) enqP <- mkEhr(0);
Ehr#(3, Bit#(TLog#(n))) deqP <- mkEhr(0);
Ehr#(3, Bool) empty <- mkEhr(True);
Ehr#(3, Bool) full <- mkEhr(False);
Bit#(TLog#(n)) max_index = fromInteger(valueOf(n)-1);
method Bool notFull = True;
method Action enq(t x);
data[enqP[0]] <= x;
empty[1] <= False;
let next_enqP = (enqP[0] == max_index) ? 0 : enqP[0] + 1;
enqP[0] <= next_enqP;
if (full[1]) begin
deqP[1] <= next_enqP;
end
else if( next_enqP == deqP[1] ) begin
full[1] <= True;
end
endmethod
method Bool notEmpty = !empty[0];
method Action deq if( !empty[0] );
full[0] <= False;
let next_deqP = (deqP[0] == max_index) ? 0 : deqP[0] + 1;
deqP[0] <= next_deqP;
if( next_deqP == enqP[0] ) begin
empty[0] <= True;
end
endmethod
method t first if( !empty[0] );
return data[deqP[0]];
endmethod
method Action clear;
enqP[1] <= 0;
deqP[2] <= 0;
empty[2] <= True;
full[2] <= False;
endmethod
endmodule