Add revocation 3.0 bits

src_Core/CPU/CsrFile.bsv

@@ -531,6 +531,8 @@ module mkCsrFile #(Data hartid)(CsrFile);
 
     // mtval (mbadaddr in spike)
     Reg#(Data) mtval_csr <- mkCsrReg(0);
+    // Capability cause register
+    Reg#(Data) mccsr_csr <- mkReadOnlyReg(64'b11);
     // mip
     Vector#(4, Reg#(Bit#(1))) external_int_pend_vec = replicate(readOnlyReg(0));
     external_int_pend_vec[prvU] <- mkCsrReg(0);
@@ -641,6 +643,9 @@ module mkCsrFile #(Data hartid)(CsrFile);
 
     // stval (sbadaddr in spike)
     Reg#(Data) stval_csr <- mkCsrReg(0);
+    // Capability cause register
+    Reg#(Bit#(2)) gclg_reg <- mkCsrReg(0);
+    Reg#(Data) sccsr_csr = concatReg3 (readOnlyReg(60'b0), gclg_reg, readOnlyReg(2'b11));
     // sip: restricted view of mip
     Reg#(Data) sip_csr = concatReg9(
         readOnlyReg(54'b0),
@@ -711,8 +716,6 @@ module mkCsrFile #(Data hartid)(CsrFile);
    Reg #(Data) rg_tdata1  = concatReg3 (rg_tdata1_type, rg_tdata1_dmode, rg_tdata1_data);
    Reg #(Data) rg_tdata2  <- mkConfigRegU;
    Reg #(Data) rg_tdata3  <- mkConfigRegU;
-   // Capability cause register
-   Reg #(CapException) mccsr_reg <- mkCsrReg(unpack(0));
 
 `ifdef INCLUDE_GDB_CONTROL
    // DCSR is 32b even in RV64
@@ -854,6 +857,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
             csrAddrSTVAL:      stval_csr;
             csrAddrSIP:        sip_csr;
             csrAddrSATP:       satp_csr;
+            csrAddrSCCSR:      sccsr_csr;
             // Machine CSRs
             csrAddrMSTATUS:    mstatus_csr;
             csrAddrMISA:       misa_csr;
@@ -873,7 +877,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
             csrAddrMARCHID:    marchid_csr;
             csrAddrMIMPID:     mimpid_csr;
             csrAddrMHARTID:    mhartid_csr;
-            csrAddrMCCSR:      csr_capcause(mccsr_reg);
+            csrAddrMCCSR:      mccsr_csr;
 `ifdef PERFORMANCE_MONITORING
             csrAddrMCOUNTERINHIBIT: perf_counters.inhibit;
 `endif
@@ -1286,7 +1290,9 @@ module mkCsrFile #(Data hartid)(CsrFile);
             sv39: prv < prvM && vm_mode_sv39_reg == 1,
             exeReadable: mxr_reg == 1,
             userAccessibleByS: sum_reg == 1,
-            basePPN: ppn_reg
+            basePPN: ppn_reg,
+            globalCapLoadGenU: gclg_reg[1],
+            globalCapLoadGenS: gclg_reg[0]
 `ifdef SECURITY
             , sanctum_evbase:   mevbase_csr,
             sanctum_evmask:     mevmask_csr,
@@ -1313,7 +1319,9 @@ module mkCsrFile #(Data hartid)(CsrFile);
             sv39: prv < prvM && vm_mode_sv39_reg == 1,
             exeReadable: mxr_reg == 1,
             userAccessibleByS: sum_reg == 1,
-            basePPN: ppn_reg
+            basePPN: ppn_reg,
+            globalCapLoadGenU: gclg_reg[1],
+            globalCapLoadGenS: gclg_reg[0]
 `ifdef SECURITY
             , sanctum_evbase:   mevbase_csr,
             sanctum_evmask:     mevmask_csr,

src_Core/ISA/ISA_Decls_CHERI.bsv

@@ -61,18 +61,6 @@ typedef struct {
 CSR_XCapCause noCapCause = CSR_XCapCause {cheri_exc_code: cheriExcNone,
                                           cheri_exc_reg: unpack(0)};
 
-function Bit#(64) xccsr_to_word(CSR_XCapCause xccsr);
-    return zeroExtend({xccsr.cheri_exc_reg, pack(xccsr.cheri_exc_code), 3'b0, 1'b1, 1'b1});
-endfunction
-
-function Reg#(Bit#(64)) csr_capcause(Reg#(CSR_XCapCause) r);
-    return (interface Reg;
-        method Bit#(64) _read = xccsr_to_word(r._read);
-        method Action _write(Bit#(64) x) =
-            r._write(CSR_XCapCause{cheri_exc_reg: x[15:10], cheri_exc_code: unpack(x[9:5]) });
-    endinterface);
-endfunction
-
 // SCR map
 
 typedef struct { Bit#(5) addr; } SCR deriving(Bits, Eq);

src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv

@@ -513,6 +513,8 @@ typedef struct {
                             // mstatus.mprv), accessing page with U=1 will NOT
                             // fault
     Bit#(44) basePPN; // ppn of root page table
+    Bit#(1) globalCapLoadGenU;
+    Bit#(1) globalCapLoadGenS;
 `ifdef SECURITY
     // sanctum page walk check
     Bit#(64) sanctum_evbase;
@@ -538,7 +540,9 @@ instance DefaultValue#(VMInfo);
         sv39: False,
         exeReadable: False,
         userAccessibleByS: False,
-        basePPN: 0
+        basePPN: 0,
+        globalCapLoadGenU: 0,
+        globalCapLoadGenS: 0
 `ifdef SECURITY
         , sanctum_evbase:   maxBound,
         sanctum_evmask:     0,

src_Core/RISCY_OOO/procs/lib/TlbTypes.bsv

@@ -70,11 +70,13 @@ typedef struct {
     Bool cap_writable;
     Bool cap_readable;
     Bool cap_dirty;
+    Bool cap_read_mod;
+    Bool cap_read_gen;
 } PTEUpperType deriving (Bits, Eq, FShow);
 
 typedef struct {
     PTEUpperType pteUpperType;
-    Bit#(7) reserved;
+    Bit#(5) reserved;
     Ppn ppn;
     Bit#(2) reserved_sw; // reserved for supervisor software
     PTEType pteType;
@@ -240,6 +242,24 @@ function TlbPermissionCheck hasVMPermission(
                 !(pte_type.executable && vm_info.exeReadable)) begin
                 fault = True;
             end
+            if (cap) begin
+                // check for invalid PTE encodings
+                if ((!pte_upper_type.cap_readable && pte_upper_type.cap_read_gen) ||
+                    (pte_upper_type.cap_readable && !pte_upper_type.cap_read_mod &&
+                    pte_upper_type.cap_read_gen)) begin
+                    fault = True;
+                end
+                // load traps if page not cap readable and using cap_read_mod set
+                if (!pte_upper_type.cap_readable && pte_upper_type.cap_read_mod) begin
+                    fault = True;
+                end
+                // perform generation check
+                if (pte_upper_type.cap_read_mod
+                    && (pte_type.user ? vm_info.globalCapLoadGenU : vm_info.globalCapLoadGenS)
+                       != pack(pte_upper_type.cap_read_gen)) begin
+                    fault = True;
+                end
+            end
         end
         DataStore: begin
             excCode = excStorePageFault;