Experimentally increase delay before reset.

This commit is contained in:
Jonathan Woodruff
2022-03-21 10:13:48 +00:00
parent 09db91f8c8
commit 3cdc2d31c8

View File

@@ -74,7 +74,7 @@ module mkRas(ReturnAddrStack) provisos(NumAlias#(TExp#(TLog#(RasEntries)), RasEn
Bool invalidHead = !(valids[head[0]][0]);
Reg#(Bit#(6)) delay <- mkReg(0);
rule resetValidHead;
if (delay < 10 && invalidHead) delay <= delay + 1;
if (delay < 32 && invalidHead) delay <= delay + 1;
else begin
valids[head[0]][2] <= True;
delay <= 0;