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Fix RVFI_DII build in the presence of 2-byte bundles.

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jon
2020-07-24 17:28:46 +01:00
parent 1f968b0c07
commit 40af067a71
1 changed files with 3 additions and 3 deletions
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6
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -87,12 +87,12 @@ import CPU_Decode_C :: *;
`ifdef RVFI_DII
interface RvfiDiiServer;
interface Client#(Dii_Parcel_Id, Dii_Parcels) toCore;
interface Server#(Dii_Parcel_Id, Vector#(SupSize, Maybe#(Instruction))) fromDii;
interface Server#(Dii_Parcel_Id, Vector#(SupSizeX2, Maybe#(Instruction16))) fromDii;
endinterface
module mkRvfiDiiServer(RvfiDiiServer);
Fifo#(2, Dii_Parcel_Id) reqs <- mkCFFifo;
Fifo#(2, Vector#(SupSize, Maybe#(Instruction))) resps <- mkCFFifo;
Fifo#(2, Vector#(SupSizeX2, Maybe#(Instruction16))) resps <- mkCFFifo;
interface Client toCore;
interface Get request = toGet(reqs);
@@ -601,7 +601,7 @@ module mkFetchStage(FetchStage);
`ifdef RVFI_DII
Dii_Parcel_Id dii_pid = dii_pid_reg[pc_fetch1_port];
dii_pid_reg[pc_fetch1_port] <= dii_pid + (fromInteger(posLastSupX2) + 1);
dii_pid_reg[pc_fetch1_port] <= dii_pid + (zeroExtend(posLastSupX2) + 1);
`endif
// Send TLB request.