Fixed a Tandem-Verification issue (report MIP change due to interrupts).

CSR MIP can change due to external/timer interrupts.  These non-instruction-related
changes were not being reported to the Tandem Verifier.

src_Core/CPU/CsrFile.bsv

@@ -90,6 +90,7 @@ interface CsrFile;
 							 Bool      init_for_way0,
 							 Bit #(5)  old_fflags,
 							 Data      old_mstatus);
+    method Data getMIP;
 `endif
 
     // The WARL transform performed during CSRRx writes to a CSR
@@ -898,6 +899,10 @@ module mkCsrFile #(Data hartid)(CsrFile);
 
        return tuple2 (new_fflags, new_mstatus);
     endmethod
+
+    method Data getMIP;
+       return mip_csr;
+    endmethod
 `endif
 
     method Data warl_xform (CSR csr, Data x);