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Fixed a Tandem-Verification issue (report MIP change due to interrupts).

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CSR MIP can change due to external/timer interrupts.  These non-instruction-related
changes were not being reported to the Tandem Verifier.
This commit is contained in:
rsnikhil
2020-03-03 18:34:00 -05:00
parent ac6043ce2d
commit 40b55d2c32
22 changed files with 35332 additions and 34109 deletions
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8
src_Core/Core/Trace_Data2.bsv
View File

@@ -24,7 +24,13 @@ import ReorderBuffer :: *;
// add to the critical path or scheduling requirements of CommitStage.
typedef struct {
Bit #(64) serial_num; // TV message serial number
// TV message serial number
Bit #(64) serial_num;
// For asynchronous CSR updates (e.g., MIP change on external interrupt)
Maybe #(Tuple2 #(Bit #(12), Data)) maybe_csr_upd;
// Remaining fields relevant only if maybe_csr_upd is Invalid
Addr pc;
Bit #(32) orig_inst; // original 16b or 32b instruction ([1:0] will distinguish 16b or 32b)
IType iType;

3
src_Core/Core/Trace_Data2_to_Trace_Data.bsv
View File

@@ -76,6 +76,9 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
if (serial_num == 0)
td = mkTrace_RESET;
else if (td2.maybe_csr_upd matches tagged Valid { .csr_addr, .csr_value })
td = mkTrace_CSR_WRITE (csr_addr, csr_value);
else if (isValid (td2.trap))
td = mkTrace_TRAP (td2.tvec,
isize,