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Some updates to build with the new bsc compiler.

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This commit is contained in:
jon
2021-02-10 17:21:35 +00:00
parent 9dd2dd9c77
commit 40ea082310
3 changed files with 40 additions and 82 deletions
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38
src_Core/CPU/CsrFile.bsv
View File

@@ -1135,7 +1135,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
tagged Interrupt .i: return mideleg_csr[pack(i)] == 1;
endcase);
// handle the trap
if(deleg) begin // handle in S mode
//if(deleg) begin // handle in S mode
// ie/prv stack
prev_prv_vec[prvS] <= prv_reg;
prv_reg <= prvS;
@@ -1165,41 +1165,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
tval: trap_val
`endif
};
end
else begin
// ie/prv stack
prev_prv_vec[prvM] <= prv_reg;
prv_reg <= prvM;
prev_ie_vec[prvM] <= ie_vec[prvM];
ie_vec[prvM] <= 0;
// record trap info
mepcc_reg[0] <= cast(pcc);
mcause_interrupt_reg <= cause_interrupt;
mcause_code_reg <= cause_code;
mtval_csr <= trap_val;
// return next pc
Data mstatus_val = fn_mstatus_val (sxl_reg, uxl_reg,
tsr_reg, tw_reg, tvm_reg,
mxr_reg, sum_reg, mprv_reg,
xs_reg, fs_reg,
/* mpp */ prv_reg, spp_reg,
/* prev_ie_vec [prvM] */ ie_vec [prvM],
prev_ie_vec [prvS],
prev_ie_vec [prvU],
/* ie_vec [prvM] */ 0,
ie_vec [prvS],
ie_vec [prvU]);
Data mcause_val = fn_mcause_val (cause_interrupt, cause_code);
return Trap_Updates {new_pcc: getNextPcc(cast(mtcc_reg))
`ifdef INCLUDE_TANDEM_VERIF
, prv: prvM,
status: mstatus_val,
cause: mcause_val,
epcc: pcc,
tval: trap_val
`endif
};
end
//end
// XXX yield load reservation should be done outside this method
endmethod

51
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -730,15 +730,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
end
`endif
Bool debugger_halt = False;
`ifdef INCLUDE_GDB_CONTROL
if ((trap.trap == tagged Interrupt intrDebugHalt)
|| (trap.trap == tagged Interrupt intrDebugStep)
|| ((trap.trap == tagged Exception excBreakpoint) && (csrf.dcsr_break_bit == 1'b1)))
begin
debugger_halt = True;
// Flush everything (tlbs, caches, reservation, branch predictor);
// reconcilei and I; update VM info.
makeSystemConsistent_for_debug_mode;
@@ -754,6 +750,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
// Tell fetch stage to wait for redirect
// Note: rule doCommitTrap_flush may have done this already; redundant call is ok.
// Or not? These apparently conflict with redirectPC now?
inIfc.setFetchWaitRedirect;
inIfc.setFetchWaitFlush;
@@ -762,39 +759,39 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
if (verbosity >= 2)
$display ("%0d: %m.commitStage.doCommitTrap_handle; debugger halt:", cur_cycle);
end
end else begin
`endif
if (! debugger_halt) begin
// trap handling & redirect
let trap_updates <- csrf.trap(trap.trap, cast(trap.pc), trap.addr, trap.orig_inst);
CapPipe new_pc = cast(trap_updates.new_pcc);
inIfc.redirectPc(cast(new_pc)
// trap handling & redirect
let trap_updates <- csrf.trap(trap.trap, cast(trap.pc), trap.addr, trap.orig_inst);
CapPipe new_pc = cast(trap_updates.new_pcc);
inIfc.redirectPc(cast(new_pc)
`ifdef RVFI_DII
, trap.x.dii_pid + (is_16b_inst(trap.orig_inst) ? 1 : 2)
, trap.x.dii_pid + (is_16b_inst(trap.orig_inst) ? 1 : 2)
`endif
);
);
`ifdef RVFI
Rvfi_Traces rvfis = replicate(tagged Invalid);
rvfis[0] = genRVFI(trap.x, traceCnt, getTSB(), getAddr(new_pc));
rvfiQ.enq(rvfis);
traceCnt <= traceCnt + 1;
Rvfi_Traces rvfis = replicate(tagged Invalid);
rvfis[0] = genRVFI(trap.x, traceCnt, getTSB(), getAddr(new_pc));
rvfiQ.enq(rvfis);
traceCnt <= traceCnt + 1;
`endif
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (way0, rg_serial_num,
tagged Invalid,
x, no_fflags, no_mstatus, tagged Valid trap_updates, no_ret_updates);
fa_to_TV (way0, rg_serial_num,
tagged Invalid,
x, no_fflags, no_mstatus, tagged Valid trap_updates, no_ret_updates);
`endif
rg_serial_num <= rg_serial_num + 1;
rg_serial_num <= rg_serial_num + 1;
// system consistency
// TODO spike flushes TLB here, but perhaps it is because spike's TLB
// does not include prv info, and it has to flush when prv changes.
// XXX As approximation, Trap may cause context switch, so flush for
// security
makeSystemConsistent(False, True, False);
// system consistency
// TODO spike flushes TLB here, but perhaps it is because spike's TLB
// does not include prv info, and it has to flush when prv changes.
// XXX As approximation, Trap may cause context switch, so flush for
// security
makeSystemConsistent(False, True, False);
`ifdef INCLUDE_GDB_CONTROL
end
`endif
endrule
// commit misspeculated load

33
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
View File

@@ -471,14 +471,11 @@ module mkFetchStage(FetchStage);
// Since CSR may be modified, sending wrong path request to TLB may cause problem
// So we stall until the next redirection happens
// The next redirect is either by the trap/system inst or an older one
Reg#(Bool) waitForRedirect <- mkReg(False);
// We don't want setWaitForRedirect method and redirect method to happen together
// make them conflict
RWire#(void) setWaitRedirect_redirect_conflict <- mkRWire;
Ehr#(3, Bool) waitForRedirect <- mkEhr(False);
// Stall fetch during the flush triggered by the procesing trap/system inst in commit stage
// We stall until the flush is done
Reg#(Bool) waitForFlush <- mkReg(False);
Ehr#(3, Bool) waitForFlush <- mkEhr(False);
Ehr#(4, CapMem) pc_reg <- mkEhr(nullCap);
`ifdef RVFI_DII
@@ -564,7 +561,7 @@ module mkFetchStage(FetchStage);
// there is no FIFO between doFetch1 and TLB, when OOO commit stage wait
// TLB idle to change VM CSR / signal flush TLB, there is no wrong path
// request afterwards to race with the system code that manage paget table.
rule doFetch1(started && !waitForRedirect && !waitForFlush);
rule doFetch1(started && !(waitForRedirect[0]) && !(waitForFlush[0]));
let pc = pc_reg[pc_fetch1_port];
// Chain of prediction for the next instructions
@@ -1108,7 +1105,7 @@ module mkFetchStage(FetchStage);
// (1) Fetch1 is stalled for waiting flush
// (2) all internal FIFOs are empty (the output sup fifo needs not to be
// empty, but why leave this security hole)
Bool empty_for_flush = waitForFlush &&
Bool empty_for_flush = waitForFlush[0] &&
!f12f2.notEmpty && !f22f3.notEmpty &&
!f32d.notEmpty && out_fifo.internalEmpty;
@@ -1131,16 +1128,15 @@ module mkFetchStage(FetchStage);
dii_pid_reg[0] <= dii_pid;
`endif
started <= True;
waitForRedirect <= False;
waitForFlush <= False;
waitForRedirect[0] <= False;
waitForFlush[0] <= False;
endmethod
method Action stop();
started <= False;
endmethod
method Action setWaitRedirect;
waitForRedirect <= True;
setWaitRedirect_redirect_conflict.wset(?); // conflict with redirect
waitForRedirect[0] <= True;
endmethod
method Action redirect(
CapMem new_pc
@@ -1157,23 +1153,22 @@ module mkFetchStage(FetchStage);
f_main_epoch <= (f_main_epoch == fromInteger(valueOf(NumEpochs)-1)) ? 0 : f_main_epoch + 1;
ehr_pending_straddle[1] <= tagged Invalid;
// redirect comes, stop stalling for redirect
waitForRedirect <= False;
setWaitRedirect_redirect_conflict.wset(?); // conflict with setWaitForRedirect
waitForRedirect[1] <= False;
// this redirect may be caused by a trap/system inst in commit stage
// we conservatively set wait for flush TODO make this an input parameter
waitForFlush <= True;
waitForFlush[2] <= True;
endmethod
`ifdef INCLUDE_GDB_CONTROL
method Action setWaitFlush;
waitForFlush <= True;
waitForFlush[1] <= True;
// $display ("%0d.%m.setWaitFlush", cur_cycle);
endmethod
`endif
method Action done_flushing() if (waitForFlush);
method Action done_flushing() if (waitForFlush[0]);
// signal that the pipeline can resume fetching
waitForFlush <= False;
waitForFlush[0] <= False;
if (verbose) $display("%t : Done Flushing",$time());
// XXX The guard prevents the readyToFetch rule in Core.bsv from firing every cycle
@@ -1221,8 +1216,8 @@ module mkFetchStage(FetchStage);
method FetchDebugState getFetchState;
return FetchDebugState {
pc: getAddr(pc_reg[0]),
waitForRedirect: waitForRedirect,
waitForFlush: waitForFlush,
waitForRedirect: waitForRedirect[0],
waitForFlush: waitForFlush[0],
mainEp: f_main_epoch
};
endmethod