Don't assume a XILINX tool flow

src_Core/RISCY_OOO/fpgautils/lib/ResetGuard.bsv

@@ -28,6 +28,9 @@ interface ResetGuard;
 endinterface
 
 `ifdef BSIM
+`define NO_XILINX
+`endif
+`ifdef NO_XILINX
 module mkResetGuard(ResetGuard);
     Reg#(Bool) ready <- mkReg(False);
 

src_Core/RISCY_OOO/fpgautils/lib/SyncFifo.bsv

@@ -24,7 +24,9 @@
 import Clocks::*;
 import FIFOF::*;
 import Assert::*;
+`ifdef USE_CONNECTAL_BRAM_SYNC_FIFO
 import ConnectalBramFifo::*;
+`endif
 import BRAMFIFO::*;
 import XilinxSyncFifo::*;
 import ResetGuard::*;

src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv

@@ -124,6 +124,9 @@ module mkXilinxIntDiv(XilinxIntDiv#(tagT)) provisos (
     Bits#(tagT, tagSz), Add#(tagSz, a__, 8)
 );
 `ifdef BSIM
+`define NO_XILINX
+`endif
+`ifdef NO_XILINX
     IntDivUnsignedImport divIfc <- mkIntDivUnsignedSim;
 `else
     IntDivUnsignedImport divIfc <- mkIntDivUnsignedImport;

src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv

@@ -110,6 +110,9 @@ module mkXilinxIntMul(XilinxIntMul#(tagT)) provisos(
     // different multilpliers: WaitAutoReset is not needed, since mul is a
     // pipeline with fixed latency
 `ifdef BSIM
+`define NO_XILINX
+`endif
+`ifdef NO_XILINX
     IntMulImport mulSigned <- mkIntMulSim(Signed);
     IntMulImport mulUnsigned <- mkIntMulSim(Unsigned);
     IntMulImport mulSignedUnsigned <- mkIntMulSim(SignedUnsigned);

src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv

@@ -79,10 +79,18 @@
 `define LOG_L2_TLB_4KB_WAYS 2 // L2 4KB TLB log ways (4 ways)
 
 // FMA bookkeeping FIFO: add 1 to allow simultaneous enq/deq
+`ifdef USE_XILINX_FPU
 `define BOOKKEEPING_FP_FMA_SIZE TAdd#(`XILINX_FP_FMA_LATENCY, 1)
+`else
+`define BOOKKEEPING_FP_FMA_SIZE 4
+`endif
 // INT MUL bookkeeping FIFO: add 1 to allow simultaneous enq/deq, another 1
 // because of internal flow control in MUL unit
+`ifdef USE_XILINX_FPU
 `define BOOKKEEPING_INT_MUL_SIZE TAdd#(`XILINX_INT_MUL_LATENCY, 2)
+`else
+`define BOOKKEEPING_INT_MUL_SIZE 4
+`endif
 
 // non-blocking DTLB
 `define DTLB_REQ_NUM 4