Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Move mux out of Reorder buffer rows into Alu Pipelines.

Browse Source
This commit is contained in:
jon
2020-07-13 12:10:41 +01:00
parent eeb6c91b9d
commit 4792581d8c
2 changed files with 11 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
View File

@@ -101,7 +101,7 @@ typedef struct {
Bool isCompressed;
// result
CapPipe data; // alu compute result
Maybe#(CapMem) csrData; // data to write CSR file
PPCVAddrCSRData csrData; // data to write CSR file, or predicted next PC if not. (For reorder buffer)
ControlFlow controlFlow;
Maybe#(CSR_XCapCause) capException;
Maybe#(BoundsCheck) check;
@@ -171,8 +171,7 @@ interface AluExeInput;
`ifdef INCLUDE_TANDEM_VERIF
CapPipe dst_data,
`endif
Maybe#(CapMem) csrData,
ControlFlow cf,
PPCVAddrCSRData csrData,
Maybe#(CSR_XCapCause) capCause
`ifdef RVFI
, ExtraTraceBundle tb
@@ -345,7 +344,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
dpTrain: x.dpTrain,
isCompressed: x.orig_inst[1:0] != 2'b11,
data: exec_result.data,
csrData: is_scr_or_csr ? Valid (exec_result.csrData) : tagged Invalid,
csrData: is_scr_or_csr ? CSRData (exec_result.csrData) : PPC (cast(exec_result.controlFlow.nextPc)),
capException: exec_result.capException,
check: exec_result.boundsCheck,
`ifdef RVFI
@@ -387,7 +386,6 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
x.data,
`endif
x.csrData,
x.controlFlow,
x.capException
`ifdef RVFI
, x.traceBundle

23
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
View File

@@ -130,8 +130,7 @@ interface Row_setExecuted_doFinishAlu;
`ifdef INCLUDE_TANDEM_VERIF
CapPipe dst_data,
`endif
Maybe#(CapMem) csrData,
ControlFlow cf,
PPCVAddrCSRData csrData,
Maybe#(CSR_XCapCause) cause
`ifdef RVFI
, ExtraTraceBundle tb
@@ -300,8 +299,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
`ifdef INCLUDE_TANDEM_VERIF
CapPipe dst_data,
`endif
Maybe#(CapMem) csrData,
ControlFlow cf,
PPCVAddrCSRData csrDataOrPPC,
Maybe#(CSR_XCapCause) cause
`ifdef RVFI
, ExtraTraceBundle tb
@@ -315,11 +313,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
`endif
// update PPC or csrData (vaddr is always useless for ALU results)
if(csrData matches tagged Valid .d) begin
ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= CSRData (d);
end else begin
ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= PPC (cast(cf.nextPc));
end
ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= csrDataOrPPC;
if (cause matches tagged Valid .exp &&& !isValid(trap[trap_finishAlu_port(i)])) begin
trap[trap_finishAlu_port(i)] <= Valid (CapException (exp));
tval[trap_finishAlu_port(i)] <= tval[trap_finishAlu_port(i)];
@@ -328,7 +322,9 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
//$display("%t : traceBundle = ", $time(), fshow(tb), " in Row_setExecuted_doFinishAlu for %x", pc);
traceBundle[trap_finishAlu_port(i)] <= tb;
`endif
doAssert((isValid(csr) || isValid(scr)) == isValid(csrData), "csr valid should match");
Bool isCsrData = False;
if (csrDataOrPPC matches tagged CSRData .unused) isCsrData = True;
doAssert((isValid(csr) || isValid(scr)) == isCsrData, "csr valid should match");
endmethod
endinterface);
end
@@ -587,8 +583,7 @@ interface ROB_setExecuted_doFinishAlu;
`ifdef INCLUDE_TANDEM_VERIF
Data dst_data,
`endif
Maybe#(CapMem) csrData,
ControlFlow cf,
PPCVAddrCSRData csrData,
Maybe#(CSR_XCapCause) cause
`ifdef RVFI
, ExtraTraceBundle tb
@@ -1140,8 +1135,7 @@ module mkSupReorderBuffer#(
`ifdef INCLUDE_TANDEM_VERIF
Data dst_data,
`endif
Maybe#(CapMem) csrData,
ControlFlow cf,
PPCVAddrCSRData csrData,
Maybe#(CSR_XCapCause) cause
`ifdef RVFI
, ExtraTraceBundle tb
@@ -1154,7 +1148,6 @@ module mkSupReorderBuffer#(
dst_data,
`endif
csrData,
cf,
cause
`ifdef RVFI
, tb