Cheri-research/Toooba
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Made the hash size in the BTB configurable

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The current configuration is a tag of 16 bits width
This commit is contained in:
Franz Fuchs
2021-03-31 17:46:27 +01:00
parent 84271b2712
commit 4b531fac46
2 changed files with 16 additions and 6 deletions
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2
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -373,7 +373,7 @@ module mkFetchStage(FetchStage);
// Can the fifo size be smaller?
// Branch Predictors
NextAddrPred nextAddrPred <- mkBtb;
NextAddrPred#(16) nextAddrPred <- mkBtbSmall;
let dirPred <- mkDirPredictor;
ReturnAddrStack ras <- mkRas;
// Wire to train next addr pred (NAP)

20
src_Core/RISCY_OOO/procs/lib/Btb.bsv
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@@ -45,8 +45,9 @@ import CHERICap::*;
export NextAddrPred(..);
export mkBtb;
export mkBtbSmall;
interface NextAddrPred;
interface NextAddrPred#(numeric type hashSz);
method Action put_pc(CapMem pc);
interface Vector#(SupSizeX2, Maybe#(CapMem)) pred;
method Action update(CapMem pc, CapMem brTarget, Bool taken);
@@ -64,7 +65,7 @@ typedef Bit#(TLog#(SupSizeX2)) BtbBank;
typedef TDiv#(TDiv#(BtbEntries,SupSizeX2),BtbAssociativity) BtbIndices;
typedef Bit#(TLog#(BtbIndices)) BtbIndex;
typedef Bit#(TSub#(TSub#(TSub#(AddrSz,SizeOf#(BtbBank)), SizeOf#(BtbIndex)), PcLsbsIgnore)) BtbTag;
typedef Bit#(16) HashedTag;
typedef Bit#(hashSz) HashedTag#(numeric type hashSz);
typedef struct {
BtbTag tag;
@@ -84,10 +85,19 @@ typedef struct {
} VnD#(type data) deriving(Bits, Eq, FShow);
(* synthesize *)
module mkBtb(NextAddrPred);
module mkBtbSmall(NextAddrPred#(16));
NextAddrPred#(16) btb <- mkBtb;
return btb;
endmodule
//(* synthesize *)
module mkBtb(NextAddrPred#(hashSz))
provisos (NumAlias#(tagSz, TSub#(TSub#(TSub#(AddrSz,SizeOf#(BtbBank)), SizeOf#(BtbIndex)), PcLsbsIgnore)),
Add#(1, a__, TDiv#(tagSz, hashSz)),
Add#(b__, tagSz, TMul#(TDiv#(tagSz, hashSz), hashSz)));
// Read and Write ordering doesn't matter since this is a predictor
Reg#(BtbBank) firstBank_reg <- mkRegU;
Vector#(SupSizeX2, MapSplit#(HashedTag, BtbIndex, VnD#(CapMem), BtbAssociativity))
Vector#(SupSizeX2, MapSplit#(HashedTag#(hashSz), BtbIndex, VnD#(CapMem), BtbAssociativity))
records <- replicateM(mkMapLossyBRAM);
RWire#(BtbUpdate) updateEn <- mkRWire;
@@ -95,7 +105,7 @@ module mkBtb(NextAddrPred);
function BtbBank getBank(CapMem pc) = getBtbAddr(pc).bank;
function BtbIndex getIndex(CapMem pc) = getBtbAddr(pc).index;
function BtbTag getTag(CapMem pc) = getBtbAddr(pc).tag;
function MapKeyIndex#(HashedTag,BtbIndex) lookupKey(CapMem pc) =
function MapKeyIndex#(HashedTag#(hashSz),BtbIndex) lookupKey(CapMem pc) =
MapKeyIndex{key: hash(getTag(pc)), index: getIndex(pc)};
// no flush, accept update