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Introduced new build flag for transient-execution testing contracts

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This commit is contained in:
Franz Fuchs
2021-07-08 15:28:54 +01:00
parent 2eb2202acd
commit 4ba377366a
7 changed files with 53 additions and 11 deletions
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1
builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/Makefile
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@@ -43,6 +43,7 @@ BSC_COMPILATION_FLAGS += \
-D RISCV \
-D RVFI_DII \
-D RVFI \
-D CONTRACTS_VERIFY \
# Default ISA test

13
src_Core/CPU/Core.bsv
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@@ -307,6 +307,7 @@ module mkCore#(CoreId coreId)(Core);
ReorderBufferSynth rob <- mkReorderBufferSynth;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
Vector#(SupSize, Bag#(16, CapMem, CapMem)) bags;
for(Integer i = 0; i < valueof(SupSize); i=i+1) begin
bags[i] <- mkSmallBag;
@@ -315,6 +316,7 @@ module mkCore#(CoreId coreId)(Core);
for(Integer i = 0; i < valueof(SupSize); i=i+1) begin
returnBags[i] <- mkSmallBag;
end
`endif
`endif
// We have two scoreboards: one conservative and other aggressive
@@ -437,6 +439,7 @@ module mkCore#(CoreId coreId)(Core);
method correctSpec = globalSpecUpdate.correctSpec[finishAluCorrectSpecPort(i)].put;
method doStats = doStatsReg._read;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
method Bool checkTarget(CapMem ppc);
Bool ret = False;
for(Integer j = 0; j < valueof(SupSize); j=j+1) begin
@@ -451,6 +454,7 @@ module mkCore#(CoreId coreId)(Core);
end
return ret;
endmethod
`endif
`endif
endinterface);
aluExe[i] <- mkAluExePipeline(aluExeInput);
@@ -505,8 +509,10 @@ module mkCore#(CoreId coreId)(Core);
method writeRegFile = writeCons(memWrConsPort);
method doStats = doStatsReg._read;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
method rob_getPredPC = rob.getOrigPredPC[valueof(AluExeNum)].get; // last getOrigPredPC port
method rob_getOrig_Inst = rob.getOrig_Inst[valueof(AluExeNum)].get; // last getOrig_Inst port
`endif
`endif
endinterface);
let memExe <- mkMemExePipeline(memExeInput);
@@ -709,6 +715,7 @@ module mkCore#(CoreId coreId)(Core);
endmethod
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
method Action updateTargets(Vector#(SupSize, Maybe#(CapMem)) targets);
for(Integer i = 0; i < valueof(SupSize); i=i+1) begin
if(targets[i] matches tagged Valid .tar) begin
@@ -725,6 +732,7 @@ module mkCore#(CoreId coreId)(Core);
end
endmethod
`endif
`endif
`ifdef INCLUDE_TANDEM_VERIF
interface v_to_TV = map (toPut, v_f_to_TV);
@@ -1171,8 +1179,8 @@ module mkCore#(CoreId coreId)(Core);
Vector #(32, Bit #(Report_Width)) tgc_evts_vec = to_large_vector (events_tgc_reg);
EventsCache llMem = unpack(pack(events_llc_reg) | pack(l2Tlb.events));
Vector #(16, Bit #(Report_Width)) llc_evts_vec = to_large_vector (llMem);
//Vector #(16, Bit #(Report_Width)) trans_exe_evts_vec = to_large_vector (renameStage.events);
`ifdef CONTRACTS_VERIFY
EventsTransExe transExe = renameStage.events;
SupCnt wildJumps = 0;
SupCnt wildExceptions = 0;
@@ -1185,13 +1193,16 @@ module mkCore#(CoreId coreId)(Core);
transExe.evt_WILD_JUMP = wildJumps;
transExe.evt_WILD_EXCEPTION = wildExceptions;
Vector #(16, Bit #(Report_Width)) trans_exe_evts_vec = to_large_vector (transExe);
`endif
let events = append (null_evt, core_evts_vec);
events = append (events, imem_evts_vec);
events = append (events, dmem_evts_vec);
events = append (events, tgc_evts_vec);
events = append (events, llc_evts_vec);
`ifdef CONTRACTS_VERIFY
events = append (events, trans_exe_evts_vec);
`endif
(* fire_when_enabled, no_implicit_conditions *)
rule rl_send_perf_evts;

14
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
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@@ -201,11 +201,13 @@ interface AluExeInput;
method Bool doStats;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
// check previous branch targets
method Bool checkTarget(CapMem ppc);
// check (previous) return targets
method Bool checkReturnTarget(CapMem ppc);
`endif
`endif
endinterface
interface AluExePipeline;
@@ -216,8 +218,10 @@ interface AluExePipeline;
method Data getPerf(ExeStagePerfType t);
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
method EventsTransExe events;
`endif
`endif
endinterface
module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
@@ -237,8 +241,10 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
Integer finishSendBypassPort = 1;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
Array#(Reg#(EventsTransExe)) events_reg <- mkDRegOR(2, unpack(0));
`endif
`endif
`ifdef PERF_COUNT
// performance counters
@@ -303,6 +309,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
let orig_inst = inIfc.rob_getOrig_Inst (x.tag);
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
let ppc_addr = getAddr(ppc);
let pc_addr = getAddr(pc);
EventsTransExe events = unpack(0);
@@ -327,7 +334,8 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
events.evt_WILD_JUMP = 1;
events_reg[1] <= events;
end
end
end
`endif
`endif
// go to next stage
@@ -444,6 +452,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
);
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
// get PC and PPC
let pc = getAddr(x.controlFlow.pc);
let ppc = getAddr(x.controlFlow.nextPc);
@@ -456,6 +465,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
events.evt_WILD_EXCEPTION = 1;
events_reg[0] <= events;
end
`endif
`endif
// handle spec tags for branch predictions
@@ -532,7 +542,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
endmethod
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
method events = events_reg[0];
`endif
`endif
endmodule

16
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
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@@ -133,11 +133,13 @@ interface CommitInput;
method Bool checkDeadlock;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
// update branch targets
method Action updateTargets(Vector#(SupSize, Maybe#(CapMem)) targets);
// update return targets
method Action updateReturnTargets(Vector#(SupSize, Maybe#(CapMem)) returnTargets);
`endif
`endif
`ifdef INCLUDE_TANDEM_VERIF
interface Vector #(SupSize, Put #(Trace_Data2)) v_to_TV;
@@ -1096,16 +1098,20 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
`endif
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
// update targets vector
Vector#(SupSize, Maybe#(CapMem)) targets;
// update return targets vector
Vector#(SupSize, Maybe#(CapMem)) returnTargets;
`endif
`endif
// compute what actions to take
for(Integer i = 0; i < valueof(SupSize); i = i+1) begin
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
Maybe#(CapMem) tar = tagged Invalid;
Maybe#(CapMem) retTar = tagged Invalid;
`endif
`endif
if(!stop && rob.deqPort[i].canDeq) begin
let x = rob.deqPort[i].deq_data;
@@ -1151,6 +1157,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
rob.deqPort[i].deq;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
// return address stack link reg is x1 or x5
function Bool linkedR(Maybe#(ArchRIndx) register);
Bool res = False;
@@ -1173,12 +1180,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
$display("RETURN target added: pc = ", fshow(x.pc), " retTar = ", fshow(retTar));
end
end
// update target
/*else if((x.iType == CJALR || x.iType == Jr) && !linkedR(x.dst)) begin
tar = tagged Valid x.ppc_vaddr_csrData.PPC;
$display("BRANCH target added: pc = ", fshow(x.pc), " ppc = ", fshow(tar));
end*/
`endif
`endif
// every inst here should have been renamed, commit renaming
@@ -1257,8 +1259,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
end
end
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
targets[i] = tar;
returnTargets[i] = retTar;
`endif
`endif
end
rg_serial_num <= rg_serial_num + instret;

10
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -222,9 +222,11 @@ interface MemExeInput;
method Bool doStats;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
method CapMem rob_getPredPC(InstTag t);
method Bit #(32) rob_getOrig_Inst (InstTag t);
`endif
`endif
endinterface
interface MemExePipeline;
@@ -242,8 +244,10 @@ interface MemExePipeline;
method Data getPerf(ExeStagePerfType t);
`ifdef PERFORMANCE_MONITORING
method EventsCoreMem events;
`ifdef CONTRACTS_VERIFY
method EventsTransExe events_trans;
`endif
`endif
endinterface
module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
@@ -285,7 +289,9 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
`ifdef PERFORMANCE_MONITORING
Array #(Reg #(EventsCoreMem)) events_reg <- mkDRegOR (5, unpack (0));
`ifdef CONTRACTS_VERIFY
Reg#(EventsTransExe) events_trans_reg <- mkDReg(unpack(0));
`endif
`endif
// reservation station
@@ -681,6 +687,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
);
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
function Bool is_16b_inst (Bit #(n) inst);
return (inst [1:0] != 2'b11);
endfunction
@@ -696,6 +703,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
events_trans.evt_WILD_EXCEPTION = 1;
events_trans_reg <= events_trans;
end
`endif
`endif
// update LSQ
@@ -1607,6 +1615,8 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
endmethod
`ifdef PERFORMANCE_MONITORING
method events = events_reg[0];
`ifdef CONTRACTS_VERIFY
method events_trans = events_trans_reg;
`endif
`endif
endmodule

4
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
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@@ -1049,7 +1049,11 @@ endfunction
function x addPc(x cap, Bit#(12) inc) provisos (Add#(f, 12, c), CHERICap::CHERICap#(x, a, b, c, d, e)) = setAddrUnsafe(cap, getAddr(cap) + signExtend(inc));
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
typedef 128 No_Of_Evts;
`else
typedef 112 No_Of_Evts;
`endif
typedef 8 Report_Width;
typedef 64 Counter_Width;
typedef 29 No_Of_Ctrs;

6
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
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@@ -645,7 +645,7 @@ interface SupReorderBuffer#(numeric type aluExeNum, numeric type fpuMulDivExeNum
// get original PC/PPC before execution, EHR port 0 will suffice
interface Vector#(TAdd#(1, aluExeNum), ROB_getOrigPC) getOrigPC;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
interface Vector#(TAdd#(1, aluExeNum), ROB_getOrigPredPC) getOrigPredPC;
interface Vector#(TAdd#(1, aluExeNum), ROB_getOrig_Inst) getOrig_Inst;
`else
@@ -1176,7 +1176,7 @@ module mkSupReorderBuffer#(
// get pc/ppc ifc used by alu exe (also one pc for mem exe)
Vector#(TAdd#(1, aluExeNum), ROB_getOrigPC) getOrigPCIfc;
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
Vector#(TAdd#(1, aluExeNum), ROB_getOrigPredPC) getOrigPredPCIfc;
`else
Vector#(aluExeNum, ROB_getOrigPredPC) getOrigPredPCIfc;
@@ -1186,7 +1186,7 @@ module mkSupReorderBuffer#(
method CapMem get(InstTag x) = row[x.way][x.ptr].getOrigPC;
endinterface);
end
`ifdef PERFORMANCE_MONITORING
`ifdef CONTRACTS_VERIFY
for(Integer i = 0; i < valueof(aluExeNum) + 1; i = i+1) begin
getOrigPredPCIfc[i] = (interface ROB_getOrigPredPC;
method CapMem get(InstTag x) = row[x.way][x.ptr].getOrigPredPC;