Cheri-research/Toooba
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Performed a bit of cleaning up

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This commit is contained in:
Franz Fuchs
2021-09-06 13:33:13 +01:00
parent 0d42b6075a
commit 4c9d89e936
3 changed files with 14 additions and 47 deletions
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1
builds/Resources/Include_Common.mk
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@@ -138,7 +138,6 @@ TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py
@echo "INFO: Re-generating CHERI tag controller parameters"
$^ -v -c $(CAPSIZE) -s $(TAGS_STRUCT:"%"=%) -a $(TAGS_ALIGN) --data-store-base-addr 0x80000000 -b $@ 0x3fffc000 0xbffff000
@echo "INFO: Re-generated CHERI tag controller parameters"
#compile: tagsparams
.PHONY: generate_hpm_vector

2
libs/RISCV_HPM_Events

Submodule libs/RISCV_HPM_Events updated: 45caf603d7...f05d22ae10

58
src_Core/CPU/Core.bsv
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@@ -63,6 +63,8 @@ import Performance::*;
`ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import BlueUtils::*;
import StatCounters::*;
import GenerateHPMVector::*;
`endif
import HasSpecBits::*;
import Exec::*;
@@ -104,8 +106,6 @@ import CHERICap::*;
import CHERICC_Fat::*;
import Bag::*;
import VnD::*;
import StatCounters::*;
import GenerateHPMVector::*;
`ifdef RVFI_DII
import Toooba_RVFI_DII_Bridge::*;
@@ -238,24 +238,6 @@ typedef enum {
} Core_Run_State
deriving (Bits, Eq, FShow);
//`ifdef PERFORMANCE_MONITORING
//instance BitVectorable #(EventsCore, SizeOf#(SupCnt), EventsCoreElements) provisos (Bits #(EventsCore, m));
// function Vector#(EventsCoreElements, SupCnt) to_vector(EventsCore e) =
// reverse(unpack(pack(e)));
//endinstance
//instance BitVectorable #(EventsCoreMem, SizeOf#(HpmRpt), EventsCoreMemElements) provisos (Bits #(EventsCoreMem, m));
// function Vector#(EventsCoreMemElements, HpmRpt) to_vector(EventsCoreMem e) =
// reverse(unpack(pack(e)));
//endinstance
//instance BitVectorable #(EventsTransExe, SizeOf#(SupCnt), EventsTransExeElements) provisos (Bits #(EventsTransExe, m));
// function Vector#(EventsTransExeElements, SupCnt) to_vector(EventsTransExe e) =
// reverse(unpack(pack(e)));
//endinstance
//instance BitVectorable #(EventsCache, SizeOf#(HpmRpt), EventsCacheElements) provisos (Bits #(EventsCache, m));
// function Vector#(EventsCacheElements, HpmRpt) to_vector(EventsCache e) =
// reverse(unpack(pack(e)));
//endinstance
//`endif
(* synthesize *)
module mkCore#(CoreId coreId)(Core);
@@ -1175,47 +1157,33 @@ module mkCore#(CoreId coreId)(Core);
hpm_core_events[1] <= events;
endrule
//Vector #(1, Bit #(Report_Width)) null_evt = replicate (0);
//Vector #(31, Bit #(Report_Width)) mem_core_evts_vec = to_large_vector (coreFix.memExeIfc.events);
//Vector #(31, Bit #(Report_Width)) other_core_evts_vec = to_large_vector (hpm_core_events[0]);
//Vector #(31, Bit #(Report_Width)) core_evts_vec = unpack(pack(mem_core_evts_vec) | pack(other_core_evts_vec));
EventsCore core_evts = unpack(pack(coreFix.memExeIfc.events) | pack(hpm_core_events[0]));
//EventsCache instMem = unpack(pack(iMem.events) | pack(iTlb.events));
EventsL1I imem_evts = unpack(pack(iMem.events) | pack(iTlb.events));
//Vector #(16, Bit #(Report_Width)) imem_evts_vec = to_large_vector (instMem);
//EventsCache dataMem = unpack(pack(dMem.events) | pack(dTlb.events));
EventsL1D dmem_evts = unpack(pack(dMem.events) | pack(dTlb.events));
//Vector #(16, Bit #(Report_Width)) dmem_evts_vec = to_large_vector (dataMem);
EventsCacheCore tgc_evts = events_tgc_reg;
//Vector #(32, Bit #(Report_Width)) tgc_evts_vec = to_large_vector (events_tgc_reg);
//EventsCache llMem = unpack(pack(events_llc_reg) | pack(l2Tlb.events));
EventsLL llmem_evts = unpack(pack(events_llc_reg) | pack(l2Tlb.events));
//Vector #(16, Bit #(Report_Width)) llc_evts_vec = to_large_vector (llMem);
let ev_struct = HPMEvents{mab_EventsCore: tagged Valid core_evts, mab_EventsL1I: tagged Valid imem_evts,
mab_EventsL1D: tagged Valid dmem_evts, mab_EventsLL: tagged Valid llmem_evts,
mab_EventsCacheCore: tagged Valid tgc_evts};
`ifdef CONTRACTS_VERIFY
EventsTransExe transExe = renameStage.events;
EventsTransExe texe_evts = renameStage.events;
SupCnt wildJumps = 0;
SupCnt wildExceptions = transExe.evt_WILD_EXCEPTION;
SupCnt wildExceptions = texe_evts.evt_WILD_EXCEPTION;
for(Integer i = 0; i < valueof(AluExeNum); i = i+1) begin
let alu_events = coreFix.aluExeIfc[i].events;
wildJumps = wildJumps + alu_events.evt_WILD_JUMP;
wildExceptions = wildExceptions + alu_events.evt_WILD_EXCEPTION;
end
transExe.evt_WILD_JUMP = wildJumps;
transExe.evt_WILD_EXCEPTION = wildExceptions;
Vector #(16, Bit #(Report_Width)) trans_exe_evts_vec = to_large_vector (transExe);
texe_evts.evt_WILD_JUMP = wildJumps;
texe_evts.evt_WILD_EXCEPTION = wildExceptions;
ev_struct = HPMEvents{mab_EventsCore: tagged Valid core_evts, mab_EventsL1I: tagged Valid imem_evts,
mab_EventsL1D: tagged Valid dmem_evts, mab_EventsLL: tagged Valid llmem_evts,
mab_EventsCacheCore: tagged Valid tgc_evts, mab_EventsTransExe: tagged Valid texe_evts};
`endif
//let events = append (null_evt, core_evts_vec);
//events = append (events, imem_evts_vec);
//events = append (events, dmem_evts_vec);
//events = append (events, tgc_evts_vec);
//events = append (events, llc_evts_vec);
//Vector#(109, Bit#(Report_Width)) events = replicate(0);
let ev_struct = HPMEvents{mab_EventsCore: tagged Valid core_evts, mab_EventsL1I: tagged Valid imem_evts,
mab_EventsL1D: tagged Valid dmem_evts, mab_EventsLL: tagged Valid llmem_evts,
mab_EventsCacheCore: tagged Valid tgc_evts};
let events = generateHPMVector(ev_struct);
`ifdef CONTRACTS_VERIFY
events = append (events, trans_exe_evts_vec);