Bumped BlueStuff and made necessary adaptations
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Submodule libs/BlueStuff updated: a8d270d79a...df2529dd42
@@ -499,13 +499,13 @@ endmodule: mkCoreW
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module mkCoreW_Synth #(Reset dm_power_on_reset)
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(CoreW_IFC_Synth #(N_External_Interrupt_Sources));
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let core <- mkCoreW (dm_power_on_reset);
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let cpu_imem_master_synth <- toAXI4_Master_Synth (core.cpu_imem_master);
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let cpu_dmem_master_synth <- toAXI4_Master_Synth (core.cpu_dmem_master);
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let cpu_imem_master_sig <- toAXI4_Master_Sig (core.cpu_imem_master);
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let cpu_dmem_master_sig <- toAXI4_Master_Sig (core.cpu_dmem_master);
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method set_verbosity = core.set_verbosity;
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method start = core.start;
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interface cpu_imem_master = cpu_imem_master_synth;
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interface cpu_dmem_master = cpu_dmem_master_synth;
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interface cpu_imem_master = cpu_imem_master_sig;
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interface cpu_dmem_master = cpu_dmem_master_sig;
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interface core_external_interrupt_sources = core.core_external_interrupt_sources;
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method nmi_req = core.nmi_req;
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`ifdef RVFI_DII
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@@ -150,11 +150,11 @@ interface CoreW_IFC_Synth #(numeric type t_n_interrupt_sources);
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// AXI4 Fabric interfaces
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// CPU IMem to Fabric master interface
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interface AXI4_Master_Synth #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
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interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
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0, 0, 0, 0, 0) cpu_imem_master;
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// CPU DMem to Fabric master interface
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interface AXI4_Master_Synth #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
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interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
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0, 0, 0, 0, 0) cpu_dmem_master;
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// ----------------------------------------------------------------
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